Gate structures for multi-gate devices

Abstract

A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor structure, comprising:
 providing a workpiece that includes:
 a first source/drain feature and a second source/drain feature, 
 a channel region sandwiched between the first source/drain feature and the second source/drain feature, 
 a dummy gate stack wrapping over the channel region, 
 a spacer layer extending along sidewalls of the dummy gate stack, and 
 a dielectric layer disposed over the first source/drain feature and the second source/drain feature; 
   selectively etching back the dielectric layer such that a top surface of the dielectric layer is lower than a top surface of the dummy gate stack;   after the selectively etching back, conformally depositing a hard mask layer over the dielectric layer;   after the conformally depositing, planarizing the substrate to form a hard mask feature over the dielectric layer;   after the planarizing, selectively removing the dummy gate stack to expose a top surface of the dummy gate stack;   depositing a gate dielectric layer over the channel region;   depositing at least one work function layer over the gate dielectric layer;   depositing a nucleation layer over the at least one work function layer using a first atomic layer deposition (ALD) process; and   depositing a metal nitride layer over the nucleation layer using a second ALD process.   
     
     
         2 . The method of  claim 1 , wherein the hard mask feature comprises a middle seam. 
     
     
         3 . The method of  claim 1 , wherein the metal nitride layer comprises a grain size smaller than 2 nm. 
     
     
         4 . The method of  claim 1 , wherein the second ALD process comprises:
 a plurality of deposition cycles, each of the plurality of deposition cycles comprising:
 a pulse of a tungsten precursor gas, 
 a pulse of a purging inert gas, and 
 a pulse of a reducing gas; and 
   at least one nitrogen plasma treatment pulse.   
     
     
         5 . The method of  claim 4 ,
 wherein the tungsten precursor gas comprises tungsten hexafluoride or tungsten pentachloride,   wherein the purging inert gas is argon,   wherein the reducing gas comprises diborane or silane.   
     
     
         6 . The method of  claim 4 , wherein the plurality of deposition cycles comprises between 2 and 8 deposition cycles. 
     
     
         7 . The method of  claim 4 , further comprising:
 after the depositing of the metal nitride layer, etching back the nucleation layer, the metal nitride layer, the at least one work function layer, and the gate dielectric layer to form a gate recess; and   depositing a self-aligned capping (SAC) dielectric layer over the gate recess.   
     
     
         8 . The method of  claim 7 , further comprising:
 before the depositing of the SAC dielectric layer, depositing a metal capping layer over the gate recess.   
     
     
         9 . A method of manufacturing a semiconductor structure, comprising:
 providing a workpiece that includes:
 a first source/drain feature and a second source/drain feature, 
 a channel region disposed between the first source/drain feature and the second source/drain feature, 
 a dummy gate stack wrapping over the channel region, 
 a spacer layer extending along sidewalls of the dummy gate stack, and 
 a dielectric layer disposed over the first source/drain feature and the second source/drain feature; 
   selectively etching back the dielectric layer such that a top surface of the dielectric layer is lower than a top surface of the dummy gate stack;   after the selectively etching back, conformally depositing a hard mask layer over the dielectric layer;   after the conformally depositing, planarizing the workpiece to form a hard mask feature over the dielectric layer;   after the planarizing, selectively removing the dummy gate stack to form a gate trench exposing the channel region;   depositing a gate dielectric layer over the channel region;   depositing at least one work function layer over the gate dielectric layer;   depositing a nucleation layer over the at least one work function layer using a first atomic layer deposition (ALD) process; and   depositing a metal nitride layer over the nucleation layer using a second ALD process,   wherein the second ALD process comprises a treatment of a plasma of a nitrogen-containing gas while the first ALD process does not.   
     
     
         10 . The method of  claim 9 , further comprising:
 after the depositing of the metal nitride layer, etching back the nucleation layer, the metal nitride layer, the at least one work function layer, and the gate dielectric layer to form a gate recess; and   depositing a metal cap layer over the gate recess.   
     
     
         11 . The method of  claim 10 , wherein a composition of the metal cap layer is different from a composition of the metal nitride layer. 
     
     
         12 . The method of  claim 10 , wherein the metal cap layer comprises tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), or ruthenium (Ru). 
     
     
         13 . The method of  claim 10 , further comprising:
 depositing a dielectric capping layer over the metal cap layer and the hard mask layer.   
     
     
         14 . The method of  claim 13 , further comprising:
 planarizing the workpiece to remove the hard mask layer.   
     
     
         15 . A method of manufacturing a semiconductor structure, comprising:
 providing a workpiece that includes:
 a fin comprising a first source/drain region, a second source/drain region, and a channel region between the first source/drain region and the second source/drain region, 
 a first source/drain feature over the first source/drain region, 
 a second source/drain feature over the second source/drain region, 
 a dummy gate stack disposed over the channel region, 
 a spacer layer extending along sidewalls of the dummy gate stack, and 
 an interlayer dielectric (ILD) layer disposed over the first source/drain feature and the second source/drain feature; 
   selectively etching back the ILD layer such that a top surface of the ILD layer is lower than a top surface of the dummy gate stack;   after the selectively etching back, conformally depositing a hard mask layer over the ILD layer;   after the conformally depositing, planarizing the workpiece to form a hard mask feature such that top surfaces of the hard mask feature and the dummy gate stack are coplanar;   selectively removing the dummy gate stack to form a gate trench exposing the channel region;   depositing a gate dielectric layer over the channel region;   depositing at least one work function layer over the gate dielectric layer;   depositing a nucleation layer over the at least one work function layer using a first atomic layer deposition (ALD) process;   depositing a metal nitride layer over the nucleation layer using a second ALD process;   etching back the metal nitride layer to form a gate top recess; and   depositing a metal cap layer over the gate top recess.   
     
     
         16 . The method of  claim 15 , wherein the first ALD process comprises:
 a first plurality of deposition cycles, each of the first plurality of deposition cycles comprising:
 a pulse of a tungsten precursor gas, 
 a pulse of a purging inert gas, and 
 a pulse of a reducing gas. 
   
     
     
         17 . The method of  claim 15 , wherein the first ALD process comprises a process temperature between about 275° C. and about 300° C. 
     
     
         18 . The method of  claim 16 , wherein the second ALD process comprises:
 a second plurality of deposition cycles, each of the second plurality of deposition cycles comprising:
 a pulse of the tungsten precursor gas, 
 a pulse of the purging inert gas, and 
 a pulse of the reducing gas; and 
   at least one plasma treatment pulse using a nitrogen-containing gas.   
     
     
         19 . The method of  claim 16 ,
 wherein the tungsten precursor gas comprises tungsten pentachloride (WCl 5 ) or tungsten hexafluoride (WF 6 ),   wherein the reducing gas comprises diborane (B 2 H 6 ), silane (SiH 4 ), hydrogen (H 2 ), or a combination thereof.   
     
     
         20 . The method of  claim 18 , wherein the nitrogen-containing gas comprises nitrogen (N 2 ), ammonia (NH 3 ), or a mixture of nitrogen (N 2 ) and hydrogen (H 2 ).