Electromagnetic interference shielding package structures and fabricating methods thereof

Abstract

The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a first die/die stack attached on a substrate;   a conductive top block including a conductive material, the conductive material attached to semiconductor material at a top surface of the first die/die stack; and   a plurality of ground wires conductively connecting the conductive top block to the substrate;   wherein the conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide electromagnetic interference shielding to the first die/die stack.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein:
 the plurality of ground wires are surrounding the first die/die stack; and   a size of the conductive top block is larger than a size of the first die/die stack in a plane substantially parallel to a major surface of the substrate, such that the top surface of the first die/die stack is completely covered by the conductive top block.   
     
     
         3 . The semiconductor structure of  claim 1 , further comprising:
 a mold compound layer on the substrate and covering the conductive top block and the plurality of ground wires; and   a plurality of solder balls attached to a bottom surface of the substrate.   
     
     
         4 . The semiconductor structure of  claim 1 , wherein the conductive material is a conductive plate having a thickness between about 20 μm and about 100 μm, the conductive top block includes:
 an insulating layer covering a top surface of the conductive plate; and 
 a plurality of bond pads embedded in the insulating layer and in electrical contact with the conductive plate. 
 
     
     
         5 . The semiconductor structure of  claim 4 , wherein:
 the conductive plate is a metal plate or a conductive polymer plate doped with a metal or a metal oxide; and   the plurality of bond pads are located adjacent to edges of the conductive top block, the bond pads having a thickness between about 0.5 μm and about 1 μm, and the bond pads having a bond pad pitch between about 50 μm and about 5 mm.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein:
 the first die/die stack is attached to the substrate by a first adhesive film; and   the conductive top block is attached to the top surface of the first die/die stack by a second adhesive film different from the first adhesive film.   
     
     
         7 . The semiconductor structure of  claim 6 , wherein:
 the first adhesive film is a die attach film; and   the second adhesive film is a film over wire penetrated by a plurality of signal wires of the first die/die stack.   
     
     
         8 . The semiconductor structure of  claim 1 , wherein the Faraday cage is a first Faraday cage, the semiconductor structure further comprising a second die/die stack without a second Faraday cage. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein the second die/die stack is located on a side of the first die/die stack in a lateral direction. 
     
     
         10 . The semiconductor structure of  claim 8 , wherein the second die/die stack includes a three-dimensional NAND Flash device, and the first die/die stack includes a memory controller to control the three-dimensional NAND Flash device. 
     
     
         11 . The semiconductor structure of  claim 8 , wherein the second die/die stack is located on a top surface of the conductive top block. 
     
     
         12 . A method of forming a semiconductor structure, comprising:
 attaching a first die/die stack on a substrate;   forming a conductive top block having a size larger than the first die/die stack;   attaching the conductive top block to cover a top surface of the first die/die stack;   forming a plurality of ground wires to conductively connect the conductive top block and the substrate, such that the conductive top block, the plurality of ground wires, and the substrate form a first Faraday cage to provide electromagnetic interference shielding of the first die/die stack; and   forming a second die/die stack located on a top surface of the conductive top block, the second die/die stack without the first Faraday cage and without a second Faraday cage.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming the plurality of ground wires surrounding the first die/die stack;   forming a mold compound layer on the substrate to cover the conductive top block and the plurality of ground wires; and   attaching a plurality of solder balls to a bottom surface of the substrate.   
     
     
         14 . The method of  claim 12 , wherein forming the conductive top block comprises:
 forming a conductive plate with a thickness between about 20 μm and about 100 μm;   forming an insulating layer covering a top surface of the conductive plate;   forming a plurality of bond pads having a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and in electrical contact with the conductive plate; and   arranging the plurality of bond pads adjacent to edges of the conductive top block, the plurality of bond pads having a bond pad pitch between about 50 μm and about 5 mm.   
     
     
         15 . The method of  claim 12 , further comprising:
 forming a conductive film having a thickness in a range from about 1 μm to about 20 μm on a top surface of a silicon wafer by spin coating, spraying, plating, or sputtering;   forming an insulating layer covering a top surface of the conductive film;   forming a plurality of bond pads having a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and in electrical contact with the conductive film; and   arranging the plurality of bond pads adjacent to edges of the conductive top block, the plurality of bond pads having a bond pad pitch between about 50 μm and about 5 mm.   
     
     
         16 . The method of  claim 12 , further comprising:
 forming at least one signal wire connecting the first die/die stack to the substrate, wherein a portion of the at least one signal wire penetrates a second adhesive film to attach the conductive top block.   
     
     
         17 . The method of  claim 12 , further comprising:
 forming a third die/die stack located on a side of the first die/die stack in a lateral direction without electromagnetic interference protection.