Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.

What is claimed is: 
     
         1 . A semiconductor device, comprising: a substrate; a gate structure disposed on the substrate; a source region and a drain region disposed within the substrate, wherein the substrate comprises a drift region laterally extending between the source region and the drain region; a first stressor layer disposed over the drift region of the substrate, wherein the first stressor layer is configured to apply a first stress to the drift region of the substrate; a second stressor layer disposed on the first stressor layer, wherein the second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress; a first contact, that changes distribution of an electric field generated by the gate structure, penetrating the second stressor layer; and a second contact electrically connected to the source region, wherein a profile of a bottom of the first contact is different from a profile of a bottom of the second contact. 
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a buffer layer disposed between the first stressor layer and the second stressor layer.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the first stressor layer has a stepped structure over the gate structure. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first stressor is configured to apply a tensile stress to the drift region of the substrate, and the second stress is configured to apply a compressive stress to the drift region of the substrate. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a density of the first stressor layer is different from a density of the second stressor layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first contact is spaced apart from the substrate. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first contact is spaced apart from the first stressor layer. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first contact has a portion tapered toward the substrate. 
     
     
         9 . The semiconductor device of  claim 1 , wherein a first dielectric layer disposed over the second stressor layer, a second dielectric layer disposed on the first dielectric layer, and a lateral surface of the first contact abutting the second dielectric layer is substantially coplanar with a lateral surface of the first contact abutting the first dielectric layer. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the first stressor layer covers the source region. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the second stressor layer is free from vertically overlapping the source region. 
     
     
         12 . A semiconductor device, comprising: a substrate having a first region and a second region, wherein the substrate has a drift region laterally extending between a first source region and a first drain region within the first region, and the substrate has a channel region extending between a second source region and a second drain region within the second region; a gate structure disposed on the substrate; a first stressor layer covers the drift region of the first region of the substrate, wherein the first stressor layer is configured to apply a first stress to the drift region of the substrate, wherein the first stressor layer further covers the channel region of the second region; a first contact, that changes distribution of an electric field generated by the gate structure, disposed over the first region of the substrate; and a second contact disposed over the second region of the substrate, wherein the first contact is spaced apart from the first stressor layer, and the second contact penetrates the first stressor layer. 
     
     
         13 . The semiconductor device of  claim 12 , further comprising:
 a second stressor layer disposed on the first stressor layer, wherein the second stressor layer is configured to apply a second stress to the drift region of the substrate, and the second stressor layer is free from vertically overlapping the channel region of the second region.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the first stress is opposite to the second stress. 
     
     
         15 . The semiconductor device of  claim 13 , further comprising:
 a buffer layer disposed between the first stressor layer and the second stressor layer.   
     
     
         16 . The semiconductor device of  claim 13 , wherein a density of the first stressor layer is different from a density of the second stressor layer. 
     
     
         17 . A semiconductor device, comprising: a substrate; a gate structure disposed on the substrate; a first source/drain region within the substrate and having a first conductive type; a well region surrounding the first source/drain region and having the first conductive type; a first stressor layer covering the well region, wherein the first stressor layer is configured to apply a first stress to the substrate; a second stressor layer disposed on the first stressor layer, wherein the second stressor layer is configured to apply a second stress to the substrate, and the first stress is opposite to the second stress; a buffer layer disposed between the first stressor layer and the second stressor layer, a first dielectric layer disposed over the second stressor layer; a first contact penetrates the first dielectric layer, the second stressor layer, and the buffer layer, wherein the first contact is spaced apart from the first stressor layer by the buffer layer. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the first stressor layer has a stepped structure over the gate structure. 
     
     
         19 . The semiconductor device of  claim 17 , further comprising: the first contact has two surfaces, a first surface and a second surface, wherein the first surface abuts the first dielectric layer and the second surface abuts the second stressor and the buffer layer. 
     
     
         20 . The semiconductor device of  claim 17 , a second dielectric layer disposed on the first dielectric layer, wherein a lateral surface of the first contact abutting the second dielectric layer is substantially coplanar with the first surface abutting the first dielectric layer.