Methods for running a high density plasma etcher to achieve reduced transistor device damage

Abstract

Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.

What is claimed is:  
     
         1 . A method for etching dielectric layers in a high density plasma etcher, comprising: 
 providing a wafer having a dielectric layer disposed over transistor devices, the transistor devices including transistor gate oxides and gate electrodes, and diffusion regions;    forming a photoresist mask over the dielectric layer in order to define at least one contact via hole over one of the diffusion regions;    inserting the wafer into the high density plasma etcher;    setting up gas flow conditions, temperature conditions and pressure conditions within the high density plasma etcher;    pulse applying a TCP power source of the high density plasma etcher; and    applying an RF bias to a bottom electrode of the high density plasma etcher;    wherein the pulse applying of the TCP power source is configured to etch through the dielectric layer to define the at least one contact via hole over one of the diffusion regions while substantially reducing damage to the transistor gate oxides of the transistor devices.    
     
     
         2 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 1 , wherein the pulse applying of the TCP power source is defined over a period T.  
     
     
         3 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 2 , wherein the period T has an on-time T ON  and an off-time T OFF , and the period T is equal to a sum of the on-time T ON  plus the off-time T OFF .  
     
     
         4 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 3 , wherein the pulse of the TCP power source has a duty cycle defined by T ON /T.  
     
     
         5 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 4 , further comprising: 
 setting the duty cycle to be between about 10 percent and about 80 percent.    
     
     
         6 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 4 , further comprising: 
 setting the period T to be between above 10 microseconds and about 2 milliseconds.    
     
     
         7 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 1 , further comprising: 
 ascertaining a desired etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;    selecting a duty cycle of the pulse application of the TCP source; and    scaling a peak power of the pulse application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source.    
     
     
         8 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 7 , wherein the scaling is designed to increase the peak power of the pulse application of the TCP source when the duty cycle is decreased.  
     
     
         9 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 7 , wherein the scaling is designed to decrease the peak power of the pulse application of the TCP source when the duty cycle is increased.  
     
     
         10 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 7 , wherein the peak power can vary between about 100 watts and about 30,000 watts.  
     
     
         11 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 3 , wherein the TCP power during the off-time T OFF  can range between being substantially off to being at a reduced power level that is less than a power level of a continuous wave power level.  
     
     
         12 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 1 , wherein the high density etcher is a TCP etching system.  
     
     
         13 . A method for etching dielectric layers in a high density plasma etcher, comprising: 
 providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole over at least one transistor diffusion region;    inserting the wafer into the high density plasma etcher;    pulse applying a TCP source of the high density plasma etcher, wherein the pulse applying includes, 
 ascertaining a desired etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;  
 selecting a duty cycle of the pulsed application of the TCP source; and  
 scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source;  
   wherein the pulsed application of the TCP source is configured to etch through the dielectric layer down to the at least one transistor diffusion region while substantially reducing damage to transistor gate oxides of transistor devices that are defined on the wafer.    
     
     
         14 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 13 , wherein the pulsed application of the TCP source is defined over a period T.  
     
     
         15 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 14 , wherein the period T has an on-time T ON  and an off-time T OFF , and the period T is equal to a sum of the on-time T ON  plus the off-time T OFF .  
     
     
         16 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 15 , wherein the duty cycle of the pulse of the TCP source is defined by T ON /T.  
     
     
         17 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 15 , further comprising: 
 setting the duty cycle to be between about 10 percent and about 80 percent,    
     
     
         18 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 17 , further comprising: 
 setting the period T to be between about 10 microseconds and about 2 milliseconds.    
     
     
         19 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 13 , wherein the peak power can vary between about 100 watts and about 30,000 watts.  
     
     
         20 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 15 , wherein the TCP power during the off-time T OFF  can range between being substantially off to being at a reduced power level that is less than a power level of a continuous wave power level.  
     
     
         21 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 13 , wherein the high density etcher is a TCP etching system.  
     
     
         22 . A high density etching system for etching layers of a semiconductor wafer, the system comprising: 
 a chamber, the chamber including, 
 a TCP source;  
 a bias source, the bias source having a surface for supporting the semiconductor wafer;  
   a TCP source and bias power controller for applying power to the TCP source and the bias source, such that the controller is configured to pulse apply power through the TCP source of the chamber.    
     
     
         23 . A high density etching system for etching layers of semiconductor wafer as recited in  claim 22 , wherein the pulsed application of the power through the TCP source is defined over a period T.  
     
     
         24 . A high density etching system for etching layers of semiconductor wafer as recited in  claim 23 , wherein the period T has an on-time T ON  and an off-time T OFF , and the period T is equal to a sum of the on-time T ON  plus the off-time T OFF .  
     
     
         25 . A high density etching system for etching layers of semiconductor wafer as recited in  claim 24 , wherein the pulse of the TCP source has a duty cycle defined by T ON /T.  
     
     
         26 . A high density etching system for etching layers of semiconductor wafer as recited in  claim 25 , wherein the duty cycle is configured to be between about 10 percent and about 80 percent.  
     
     
         27 . A high density etching system for etching layers of semiconductor wafer as recited in  claim 26 , wherein the period T is configured to be between about 10 microseconds and about 2 milliseconds.  
     
     
         28 . A method for etching dielectric layers in a high density plasma etcher, comprising: 
 providing a wafer having a photoresist mask over a dielectric layer in order to define at least one via hole or open area that is electrically interconnected down to a silicon substrate of the wafer, the dielectric layer being any layer of wafer;    inserting the wafer into the high density plasma etcher;    pulse applying a TCP source of the high density plasma etcher, wherein the pulse applying includes, 
 ascertaining a desired etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;  
 selecting a duty cycle of the pulsed application of the TCP source; and  
 scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source;  
   wherein the pulsed application of the TCP source is configured to etch the via hole through the dielectric layer while substantially reducing damage to transistor gate oxides of transistor devices formed over the wafer.    
     
     
         29 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 28 , wherein the pulsed application of the TCP source is defined over a period T.  
     
     
         30 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 29 , wherein the period T has an on-time T ON  and an off-time T OFF , and the period T is equal to a sum of the on-time T ON  plus the off-time T OFF .  
     
     
         31 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 30 , wherein the duty cycle of the pulse of the TCP source is defined by T ON /T.  
     
     
         32 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 30 , further comprising: 
 setting the duty cycle to be between about 10 percent and about 80 percent.    
     
     
         33 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 32 , further comprising: 
 setting the period T to be between about 10 microseconds and about 2 milliseconds.    
     
     
         34 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 28 , wherein the peak power can vary between about 100 watts and about 30,000 watts.  
     
     
         35 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 30 , wherein the TCP power during the off-time T OFF  can range between being substantially off to being at a reduced power level that is less than a power level of a continuous wave power level.  
     
     
         36 . A method for etching dielectric layers in a high density plasma etcher as recited in  claim 28 , wherein the high density etcher is a TCP etching system.