A 3-d microelectronic structure including a vertical thermal nitride mask

Abstract

A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is:  
     
         1 . A 3D microelectronic structure comprising: 
 a substrate having at least one opening present therein, said at least one opening having sidewalls which extend to a common bottom wall; and    a thermal nitride layer present on at least an upper portion of each sidewall of said at least one opening.    
     
     
         2 . The 3D microelectronic structure of  claim 1  wherein said substrate comprises a semiconducting material or an insulating material.  
     
     
         3 . The 3D microelectronic structure of  claim 2  wherein said substrate is a semiconducting material.  
     
     
         4 . The 3D microelectronic structure of  claim 1  wherein said opening has an elongated lower portion.  
     
     
         5 . The 3D microelectronic structure of  claim 1  wherein said opening has a lower portion which is protected by an oxide layer.  
     
     
         6 . The 3D microelectronic structure of  claim 5  wherein said oxide layer in said lower portion of said opening has a recessed resist fill material thereon.  
     
     
         7 . The 3D microelectronic structure of  claim 1  wherein said opening has a lower portion, and a buried plate is formed about said lower portion of said opening.  
     
     
         8 . The 3D microelectronic structure of  claim 1  wherein said opening has an elongated lower portion, and a buried plate is formed about said lower elongated portion of said opening.  
     
     
         9 . The 3D microelectronic structure of  claim 1  wherein said thermal nitride has a thickness of from about 10 to about 50 Å.  
     
     
         10 . A method for fabricating a 3D microelectronic structure having a thin, uniform thermal nitride formed on at least an upper portion of each expose sidewalls of at least one opening, said method comprising the steps of: 
 (a) forming at least one opening in a surface of a substrate, said at least one opening having sidewalls which extend to a common bottom wall; and    (b) forming a thermal nitride layer on at least an upper portion of each sidewall of said at least one opening.    
     
     
         11 . The method of  claim 10  wherein said at least one opening is formed by lithography and etching.  
     
     
         12 . The method of  claim 10  wherein said thermal nitride layer is formed by heating said substrate at a temperature of from about 600° to about 1200° C. in the presence of a nitrogen-containing source gas.  
     
     
         13 . The method of  claim 10  wherein prior to said forming of said thermal nitride layer a lower portion of the at least one opening is protected by an oxide layer.  
     
     
         14 . The method of  claim 13  further comprising elongating a lower portion of said opening using said thermal nitride layer has a vertical hard mask.  
     
     
         15 . The method of  claim 14  further comprising forming a buried plate about said elongated lower portion of said at least one opening.  
     
     
         16 . The method of  claim 15  wherein said buried plate is formed by a gas phase doping process.  
     
     
         17 . The method of  claim 10  further comprising forming a buried plate about a lower portion of said at least one opening using a gas phase doping process and said thermal nitride layer serves as a dopant diffusion barrier.  
     
     
         18 . The method of  claim 10  wherein a H 2  prebake process is performed prior to forming said thermal nitride layer so as to remove native oxide from said upper portion of said at least one opening.  
     
     
         19 . The method of  claim 18  wherein said H 2  prebake process is carried out at a temperature of from about 700° to about 1000° C. and at a pressure of from about 1 to about 300 Torr.  
     
     
         20 . The method of  claim 10  wherein said thermal nitride layer is formed in the presence of a nitrogen-containing radical and at a temperature from about room temperature to about 1200° C.