Method of making semiconductor devices using carbon nitride, a low-dielectric-constant hard mask and/or etch stop

Abstract

A method for making a semiconductor device using carbon nitride as an etch stop diffusion barrier and/or a hard mask is described. An interconnect structure is made by at least: forming an etch stop diffusion layer, depositing an interlayer dielectric, etching necessary vias and trenches, forming a barrier layer, forming copper alloy, and planarizing. The use of a hard mask in the method is optional. The etch stop diffusion layer, the optional hard mask, or both comprised by carbon nitride.

What is claimed is:  
     
         1 . A method of fabricating an interconnect structure in an integrated circuit comprising: 
 forming a first carbon nitride layer over an underlying layer;    depositing an interlayer dielectric on the first carbon nitride layer;    etching vias and trenches in the interlayer dielectric;    forming a barrier layer over the dielectric, so as to line the vias and the trenches;    forming a copper alloy over the barrier layer, so as to fill the vias and the trenches; and    planarizing the copper alloy.    
     
     
         2 . The method of  claim 1 , further comprising: 
 forming a second layer of carbon nitride on the upper surface of the dielectric.    
     
     
         3 . The method of  claim 1 , wherein the barrier layer includes tantalum or tantalum nitride.  
     
     
         4 . The method of  claim 1 , wherein the interlayer dielectric is a polymer layer.  
     
     
         5 . The method of  claim 1 , wherein the interlayer dielectric is a non-organic layer.  
     
     
         6 . The method of  claim 2 , further comprising: 
 removing the second layer of carbon nitride.    
     
     
         7 . The method of  claim 1 , wherein the planarizing comprises: 
 performing chemical mechanical polish (CMP).    
     
     
         8 . The method of  claim 1 , wherein the method is repeated for multi-layered structures.  
     
     
         9 . The method of  claim 2 , wherein the method is repeated for multi-layered structures.  
     
     
         10  The method of  claim 6 , wherein the method is repeated for multi-layered structures.  
     
     
         11 . A method of fabricating an interconnect structure in an integrated circuit comprising: 
 forming an etch stop/diffusion barrier over an underlying layer;    depositing an interlayer dielectric on the etch stop/diffusion barrier;    forming a carbon nitride layer over the dielectric;    etching vias and trenches in the interlayer dielectric, using the carbon nitride layer as a hard mask;    forming a barrier layer over the hard mask and dielectric, so as to line the vias and trenches;    forming a copper alloy over the barrier layer, so as to fill the vias and the trenches; and    planarizing the copper alloy.    
     
     
         12 . The method of  claim 11 , wherein the etch stop/diffusion barrier is silicon nitride.  
     
     
         13 . The method of  claim 11 , wherein the interlayer dielectric is a polymer layer.  
     
     
         14 . The method of  claim 11 , wherein the interlayer dielectric is a non-organic layer.  
     
     
         15 . The method of  claim 11 , further comprising: 
 removing the carbon nitride hard mask.    
     
     
         16 . The method of  claim 1 , wherein planarizing comprises: 
 performing chemical mechanical polish (CMP).    
     
     
         17 . The method of  claim 11 , wherein the method is repeated for multi-layered structures.  
     
     
         18 . The method of  claim 15 , wherein the method is repeated for multi-layered structures.  
     
     
         19 . An interconnect structure comprising: 
 a first layer of carbon nitride disposed on an underlying layer;    vias and trenches defined by an interlayer dielectric disposed on the first layer of carbon nitride;    a barrier layer lining the vias and the trenches; and    a copper alloy over the barrier layer, filling the vias and the trenches.    
     
     
         20 . The interconnect structure of  claim 19 , further comprising: 
 a second layer of carbon nitride disposed on the upper surface of the interlayer dielectric.    
     
     
         21 . The interconnect structure of  claim 19 , wherein the barrier layer is tantalum or tantalum nitride.  
     
     
         22 . The interconnect structure of  claim 19 , wherein the interlayer dielectric is a polymer layer.  
     
     
         23 . The interconnect structure of  claim 19 , wherein the interlayer dielectric is a non-organic layer.  
     
     
         24 . The interconnect structure of  claim 19 , wherein the structure is repeated for multilayered structures.  
     
     
         25 . The interconnect structure of  claim 20 , wherein the structure is repeated for multilayered structures.  
     
     
         26 . An interconnect structure comprising: 
 an etch stop/diffusion barrier disposed on an underlying layer;    vias and trenches defined by an interlayer dielectric disposed on the etch stop/diffusion barrier;    a carbon nitride hard mask disposed on the interlayer dielectric;    a barrier layer lining the vias and the trenches; and    a copper alloy over the barrier layer, filling the vias and the trenches.    
     
     
         27 . The interconnect structure of  claim 26 , wherein the etch stop/diffusion barrier is silicon nitride.  
     
     
         28 . The interconnect structure of  claim 26 , wherein the interlayer dielectric is a polymer layer.  
     
     
         29 . The interconnect structure of  claim 26 , wherein the interlayer dielectric is a non-organic layer.  
     
     
         30 . The interconnect structure of  claim 26 , whereby the structure is repeated for multilayered structures.