Memory expansion and chip scale stacking system and method

Abstract

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

1 . A memory access system comprising: 
 a memory expansion board;    a high-density circuit module comprised of first and second integrated circuits, the high-density circuit module being mounted on the memory expansion board;    a switching multiplexer mounted on the memory expansion board, the switching multiplexer for switching data lines between the first and second integrated circuits; and    a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.    
   
   
       2 . A memory access system comprising: 
 a high-density circuit module comprised of plural integrated circuits;    a switch for connecting a datapath to one of the plural integrated circuits of the high-density circuit module;    a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural integrated circuits in response to a combination signal comprised of a clock signal and a chip select signal.    
   
   
       3 . The memory access system of  claim 2  in which the plural integrated circuits of the high-density circuit module number four.  
   
   
       4 . The memory access system of  claim 2  in which the plural integrated circuit of the high-density circuit module number two.  
   
   
       5 . A memory access system comprising: 
 plural memory expansion boards each populated with plural high-density circuit modules, each of which plural high-density circuit modules being comprised of plural integrated circuits;    plural multiplexers mounted upon each of the plural memory expansion boards, the plural multiplexers for making connections between a datapath and single ones of the plural integrated circuits comprising the high-density circuit modules;    decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the plural integrated circuits.    
   
   
       6 . The memory access system of  claim 5  in which the multiplexers are FET multiplexers.  
   
   
       7 . The memory access system of  claim 5  in which the plural high-density circuit modules are comprised of four integrated circuits.  
   
   
       8 . The memory access system of  claim 5  in which the plural high-density circuit modules are comprised from two integrated circuits.  
   
   
       9 . The memory access system of  claim 7  in which the four integrated circuits are CSPs.  
   
   
       10 . The memory access system of  claim 8  in which the two integrated circuits are CSPs.  
   
   
       11 . A memory access system comprising: 
 a memory board having a board memory signal data connection that provides a connection for memory signals between a plurality of integrated circuits mounted on the memory board and memory control circuitry;    a high-density circuit module comprised of first, second, third, and fourth individual integrated circuits, the high-density circuit module being mounted on the memory board;    a switching multiplexer mounted on the memory board, the switching multiplexer having a set of plural input data connections, individual ones of the plural input data connections connected to provide individual data connections between each of the first, second, third, and fourth individual integrated circuits and the switching multiplexer; and    a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.    
   
   
       12 . The memory access system of  claim 11  in which the switching multiplexer further comprises an output data connection connected to the board signal memory data connection.  
   
   
       13 . The memory access system of  claim 12  in which the switching multiplexer provides selective individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits.  
   
   
       14 . The memory access system of  claim 13  in which the individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits occurs in response to the switching multiplexer control signal from the decode logic circuit.  
   
   
       15 . The memory access system of  claim 11  in which the decode logic circuit is mounted on the memory board.  
   
   
       16 . A memory access system comprising: 
 a high-density circuit module comprised of stacked plural individual integrated circuits;    a switch for individually connecting a datapath to one of the plural individual integrated circuits of the high-density circuit module at a time; and    a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural individual integrated circuits at a time.    
   
   
       17 . The memory access system of  claim 16  in which the control signal is generated from a clock signal and a chip select signal.  
   
   
       18 . The memory access system of  claim 16  in which the stacked plural integrated circuits of the high-density circuit module number four.  
   
   
       19 . The memory access system of  claim 16  in which the stacked plural integrated circuit of the high-density circuit module number two.  
   
   
       20 . A memory access system comprising: 
 X memory expansion boards each populated with Y high-density circuit modules, each of which Y high-density circuit modules being comprised of Z individual integrated circuits;    plural multiplexers mounted upon each of the X memory expansion boards, the plural multiplexers each for selectively making connections between a datapath and single ones of the Z integrated circuits comprising each of the Y high-density circuit modules;    decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the Z integrated circuits.    
   
   
       21 . The memory access system of  claim 20  in which the multiplexers are FET multiplexers.  
   
   
       22 . The memory access system of  claim 20  in which Z equals 4.  
   
   
       23 . The memory access system of  claim 20  in which Z equals 2.  
   
   
       24 . The memory access system of  claim 22  in which the four integrated circuits are CSPs.  
   
   
       25 . The memory access system of  claim 23  in which the two integrated circuits are CSPs.