US2005208753A1PendingUtilityA1
Dual-damascene interconnects without an etch stop layer by alternating ILDs
Est. expirySep 28, 2021(expired)· nominal 20-yr term from priority
H10W 20/48H10W 20/084
44
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Abstract
A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
Claims
exact text as granted — not AI-modified1 - 24 . (canceled)
25 . A method for fabricating an integrated circuit comprising:
depositing a first ILD entirely of a first material; forming vias and conductors in the first ILD; forming a second ILD directly on the first ILD entirely of a second material; etching openings in the second ILD with a first etchant that etches the second material faster than the first material; forming a third ILD entirely of the first material directly on the second ILD; and etching openings in the third ILD with a second etchant that etches the first material faster than the second material.
26 . The method defined by claim 25 wherein the second material comprises a carbon-based oxide.
27 . The method defined by claim 26 wherein the first material comprises a polymer based dielectric.
28 . The method defined by claim 27 wherein the second material is etched with a fluorocarbon.
29 . The method defined by claim 28 wherein the first material is etched with oxygen or hydrogen.
30 . The method defined by claim 25 including the steps of forming vias and conductors in the second and third ILDs.
31 . A method of fabricating an integrated circuit comprising:
forming first alternate interlayer dielectrics (ILDs) entirely of a first material; forming second ILDs intermediate between the first ILDs entirely of a second material where the second are material is etchable at a faster rate than the first material by a first etchant and where the second material is etchable at a faster rate than the first material by a second etchant.
32 . The method defined by claim 31 wherein the first material comprises an organic based material, and wherein the second material comprises a non-organic based material.
33 . The method defined by claim 32 including forming vias and conductors in each of the ILDs.
34 . The method defined by claim 33 wherein the vias and conductors are formed with a dual-damascene process.
35 . (canceled)
36 . The method defined by claim 31 wherein conductors in the first and second layer are covered by a shunting material.Cited by (0)
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