Barrier free copper interconnect by multi-layer copper seed

Abstract

A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

1 - 32 . (canceled)  
   
   
       33 . An apparatus with a barrier-free interconnect that includes copper, comprising: 
 a layer of dielectric, provided over a semiconductor substrate and having an opening therein;    an interface layer deposited over inside surfaces of the opening, the interface layer comprising at least one seed layer comprising copper alloy; and    an interconnect that includes copper provided over the interface layer.    
   
   
       34 . The apparatus of  claim 33 , the copper alloy comprising copper alloyed with a material selected from the group consisting of Cr and Pd and Sn and Ti and Zr and Mg and Al and Co.  
   
   
       35 . The apparatus of  claim 44 , wherein the seed layers have been annealed at a temperature of no less than about 350 degrees C. for a time of no less than about 10 minutes, creating a barrier-less seed layer around said interconnect.  
   
   
       36 . The apparatus of  claim 33 , a cap layer additionally having been formed over the surface of the layer of dielectric, including the surface of the created interconnect.  
   
   
       37 . The apparatus of  claim 33 , the at least one first seed layer having been deposited to a thickness between about 50 and 300 Angstrom.  
   
   
       38 . The apparatus of  claim 44 , the at least one further seed layer having been deposited to a thickness between about 300 and 800 Angstrom.  
   
   
       39 . The apparatus of  claim 36 , the cap layer comprising SiC or SiN.  
   
   
       40 . The apparatus of  claim 33 , the opening comprising a dual damascene opening.  
   
   
       41 . The apparatus of  claim 33 , the layer of dielectric comprising a low-k dielectric.  
   
   
       42 . The apparatus of  claim 33 , the interface layer having been annealed.  
   
   
       43 . (canceled)  
   
   
       44 . The apparatus of  claim 33 , wherein the interface layer includes at least one further seed layer comprising copper.  
   
   
       45 . The apparatus of  claim 33 , wherein the interconnect has been deposited over the interface layer.