US2005266666A1PendingUtilityA1

Suppression of cross diffusion and gate depletion

46
Individually held — no corporate assignee on recordPriority: Mar 15, 2001Filed: Jul 28, 2005Published: Dec 1, 2005
Est. expiryMar 15, 2021(expired)· nominal 20-yr term from priority
Inventors:Jigish TrivediZhongze WangChih-Chen ChoMike VioletteTodd R. Abbott
H10D 84/0188H10D 84/0186H10D 84/0177H10D 84/038G11C 11/412H10B 10/12H10B 10/00
46
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

Claims

exact text as granted — not AI-modified
1 . A method of forming a polysilicide gate electrode structure comprising: 
 providing a polycrystalline silicon layer having an N+ polysilicon layer portion and a P+ polysilicon layer portion;    providing an overlying metal based film layer; and    providing an oxide layer between said polycrystalline silicon layer and said metal based film layer.    
   
   
       2 . The method of  claim 1  wherein said oxide layer is formed on only said N+ polysilicon layer portion.  
   
   
       3 . The method of  claim 1  wherein said oxide layer is formed on only said P+ polysilicon layer portion.  
   
   
       4 . The method of  claim 1  wherein said oxide layer is formed on said N+ and P+ polysilicon layer portions.  
   
   
       5 . The method of  claim 1  wherein said N+ polysilicon layer portion forms a portion of a pull-down transistor and said P+ polysilicon layer portion forms a portion of a pull-up transistor.  
   
   
       6 . The method of  claim 1  wherein said N+ polysilicon layer portion forms a portion of a pull-down transistor, and said oxide layer is formed on only said N+ polysilicon layer portion.  
   
   
       7 . The method of  claim 1  wherein said P+ polysilicon layer portion forms a portion of a pull-up transistor, and said oxide layer is formed on only said P+ polysilicon layer portion.  
   
   
       8 . The method of  claim 1  wherein said oxide layer is silicon dioxide.  
   
   
       9 . The method of  claim 1  wherein said oxide layer has a thickness under 125 Å.  
   
   
       10 . The method of  claim 1  wherein said oxide layer has a thickness under 125 Å and said polycrystalline silicon layer has a thickness of under 4000 Å.  
   
   
       11 . The method of  claim 1  wherein said metal based film layer is a film layer selected from the group consisting of metals, metal silicides, and metal nitrides.  
   
   
       12 . The method of  claim 1  wherein said metal based film layer is provided only over said P+ polysilicon layer portion and wherein said oxide layer is provided only on said P+ polysilicon layer portion.  
   
   
       13 . The method of  claim 1  wherein metal based film layer is provided only over said N+ polysilicon layer portion and wherein said oxide is provided only on said N+ polysilicon layer portion.  
   
   
       14 . The method of  claim 1  further comprises providing a substrate having an N type active region, wherein said N+ polysilicon layer portion is provided over said N type active region.  
   
   
       15 . The method of  claim 1  further comprises providing a substrate having a P type active region, wherein said P+ polysilicon layer portion is provided over said P type active region.  
   
   
       16 . The method of  claim 1  further comprises providing a substrate having N type and P type active regions, wherein said N+ polysilicon layer portion is provided over said N type active region and said P+ polysilicon layer portion is provided over said P type active region.  
   
   
       17 . The method of  claim 1  further comprises: 
 providing a semiconductor substrate;    forming a P well in said semiconductor substrate;    forming an N well in said semiconductor substrate adjacent to said P well;    forming an N type active region in said P well;    forming a P type active region in said N well; and    forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region, wherein said N+ polysilicon layer portion is provided over said N type active region and said P+ polysilicon layer portion is provided over said P type active region.    
   
   
       18 . The method of  claim 1 , further comprising: 
 providing a semiconductor substrate having P and N wells;    forming an NMOS transistor having an N type active region in said P well;    forming a PMOS transistor having a P type active region in said N well; and    forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region, wherein said N+ polysilicon layer portion forms a portion of said NMOS transistor and a P+ polysilicon layer portion forms a portion of said PMOS transistor.    
   
   
       19 . The method of  claim 1 , further comprising: 
 providing a semiconductor substrate;    forming a P well in said semiconductor substrate;    forming an N well in said semiconductor substrate;    forming an NMOS transistor having an N type active region in said P well;    forming a PMOS transistor having a P type active region in said N well; and    forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region, wherein said N+ polysilicon layer portion forms a portion of said NMOS transistor, said P+ polysilicon layer portion forms a portion of said PMOS transistor, and said oxide layer is provided only over said P+ polysilicon layer portion.    
   
   
       20 . The method of  claim 1 , further comprising: 
 providing a semiconductor substrate;    forming a P well in said semiconductor substrate;    forming an N well in said semiconductor substrate;    forming an NMOS transistor having an N type active region in said P well;    forming a PMOS transistor having a P type active region in said N well; and    forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region, wherein said N+ polysilicon layer portion forms a portion of said NMOS transistor, said P+ polysilicon layer portion forms a portion of said PMOS transistor, and said oxide layer is provided only over said N+ polysilicon layer portion.    
   
   
       21 . The method of  claim 1 , further comprising: 
 providing a semiconductor substrate having P and N wells;    forming a flip-flop having two access transistors and a pair of cross coupled inverters, wherein each pair of cross-coupled inverters includes a pull up transistor and a pull down transistor, and wherein said pull-up transistor defines a P type active region in said N well and said pull-down transistor defines an N type active region in said P well; and    forming an isolation region in said semiconductor substrate to isolate said N type active region from said P type active region, wherein said N+ polysilicon layer portion forms a portion of said pull-down transistor and said P+ polysilicon layer portion forms a portion of said pull-up transistor.

Join the waitlist — get patent alerts

Track US2005266666A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.