Semiconductor integrated circuit device and method of manufacturing the same

Abstract

A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.

1 - 19 . (canceled)  
     
     
         20 . A semiconductor integrated circuit device comprising: 
 a bit line;    a write word line provided above the bit line to cross the bit line; and    a memory cell including a magnetoresistive element, the magnetoresistive element provided on the bit line and below the write word line.    
     
     
         21 . The device according to  claim 20 , further comprising: 
 a first yoke material that covers side surfaces of the write word line and extends below the write word line.    
     
     
         22 . The device according to  claim 21 , wherein the first yoke material covers an upper surface of the write word line.  
     
     
         23 . The device according to  claim 22 , wherein of the first yoke material, a portion covers the side surfaces of the write word line and extends below the write word line is formed from an insulating material, and a portion that covers the upper surface of the write word line is formed from a conductive material.  
     
     
         24 . The device according to  claim 21 , wherein the first yoke material is a conductor.  
     
     
         25 . The device according to  claim 21 , wherein the first yoke material is an insulator.  
     
     
         26 . The device according to  claim 21 , further comprising: 
 a second yoke material that covers bottom and side surfaces of the bit line.    
     
     
         27 . The device according to  claim 26 , wherein the second yoke material is not in contact with the first yoke material.  
     
     
         28 . The device according to  claim 27 , wherein a dielectric interlayer on insulates the intracell local interconnection from the bit line, the dielectric interlayer has a portion sandwiched between the second yoke material and the first yoke material.  
     
     
         29 . The device according to  claim 28 , wherein the dielectric interlayer includes a stopper layer containing an insulating material different from the dielectric interlayer, the stopper layer located on the bit line and sandwiched between the second yoke material and the first yoke material.  
     
     
         30 . The device according to  claim 20 , wherein a bottom surface of the magnetoresistive element and an upper surface of the bit line are on the same level.  
     
     
         31 . The device according to  claim 20 , wherein the magnetoresistive element is a tunnel-type magnetoresistive element.  
     
     
         32 - 38 . (canceled)