Isolation structure for strained channel transistors

Abstract

A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

1 . A strained channel transistor with at least one isolation structure, the transistor being formed on a semiconductor substrate comprising a strained silicon layer overlying a tensile strain forming buffer layer, the isolation structure comprising: 
 an active region formed in the semiconductor substrate; and    at least one nitrogen-containing liner isolation region next to the active region.    
   
   
       2 . The transistor according to  claim 1 , wherein the isolation region is a shallow trench isolation region with a trench depth in the range of 2000 to 6000 angstroms.  
   
   
       3 . The transistor according to  claim 1 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.  
   
   
       4 . The transistor according to  claim 1 , wherein a channel region is formed in the strained silicon layer of the active region with a source or drain region formed between the channel region and the isolation region.  
   
   
       5 . The transistor according to  claim 1 , wherein the tensile strain forming buffer layer is a relaxed silicon-germanium layer.  
   
   
       6 . The transistor according to  claim 5 , wherein the substrate further comprises a graded silicon-germanium buffer layer underlying the relaxed silicon-germanium layer, the graded silicon-germanium buffer layer overlying a silicon substrate.  
   
   
       7 . The transistor according to  claim 1 , wherein the isolation region further comprises an oxide liner underlying the nitrogen-containing liner.  
   
   
       8 . The transistor according to  claim 1 , wherein the isolation region includes a gap filler material.  
   
   
       9 . The transistor according to  claim 1 , wherein the nitrogen-containing liner comprises at least one of silicon nitride, silicon oxynitride, or nitrogen-doped silicon oxide.  
   
   
       10 . The transistor according to  claim 1 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).  
   
   
       11 . The transistor according to  claim 1 , wherein a in-plane tensile strain of a channel region of the active region is between 0.1% to 2%.  
   
   
       12 . A method of forming an isolation structure for strained channel transistors comprising: 
 providing a semiconductor substrate comprising a strained silicon layer overlying a strain forming buffer layer;    forming a trench in the semiconductor substrate;    forming a nitrogen-containing liner in the trench; and    filling the trench with a gap filler material,    wherein the nitrogen-containing liner reduces a compressive strain asserted on the strained silicon layer by the gap filler material contained therein.    
   
   
       13 . The method according to  claim 12 , wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.  
   
   
       14 . The method according to  claim 12 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).  
   
   
       15 . The method according to  claim 12 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.  
   
   
       16 . The method according to  claim 12 , further comprising the step of, after the step of forming the trench, of forming a silicon oxide liner underlying the nitrogen-containing liner.  
   
   
       17 . The method according to  claim 16 , wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.  
   
   
       18 . The method according to  claim 12 , further comprising the step, after the step of forming the trench, of performing a corner rounding process step.  
   
   
       19 . The method according to  claim 18 , wherein the corner rounding process step is an anneal at a temperature in the range of 700 to 950 degrees Celsius in a gaseous ambient, the gaseous ambient.  
   
   
       20 . The method according to  claim 18 , further comprising a step, after the step of corner rounding, of forming a silicon oxide liner.  
   
   
       21 . The method according to  claim 18 , wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.  
   
   
       22 . The method according to  claim 18 , wherein forming the trench in the semiconductor substrate further includes forming a pull back of the opening of the trench.  
   
   
       23 . The method according to  claim 22 , wherein the pull back is in the range of 50 to 1000 angstroms.  
   
   
       24 . The method according to  claim 22 , wherein the pull back is formed by a chemical treatment with a wet etch process in hot acid at a temperature in the range of 150 to 180 degrees Celsius.  
   
   
       25 . The method according to  claim 24 , wherein the chemical treatment further includes a wet etch process in dilute hydrochloric acid.