Thick metal layer integrated process flow to improve power delivery and mechanical buffering

Abstract

A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C 4 ) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

1 . A method comprising: 
 forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die;    forming a first dielectric layer over the first metal layer;    forming vias in the first dielectric layer;    forming a second base layer metallization in the vias of the first dielectric layer; and    forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being adapted to transfer current from the bumps to the top metal layer of the integrated circuit die.    
     
     
         2 . The method of  claim 1 , wherein the first and second bumps are Controlled Collapse Chip Connection bumps.  
     
     
         3 . The method of  claim 1 , wherein the first metal layer is about 10 to 50 microns thick.  
     
     
         4 . The method of  claim 1 , wherein said forming the first metal layer over the first base layer metallization comprises electroplating copper to the first base layer metallization.  
     
     
         5 . The method of  claim 1 , further comprising attaching the bumps to solder bumps of a substrate.  
     
     
         6 . The method of  claim 1 , further comprising forming the first base layer metallization in vias of a polyimide layer.  
     
     
         7 . The method of  claim 1 , further comprising forming the first base layer metallization in vias of a benzocyclobutene layer.  
     
     
         8 . The method of  claim 1 , further comprising forming the first base layer metallization in vias of an epoxy layer.  
     
     
         9 . The method of  claim 1 , wherein said forming a first dielectric layer uses a self-planarizing, photo-definable polymer.  
     
     
         10 . The method of  claim 1 , wherein said forming a first dielectric layer uses a self-planarizing, non-photo-definable polymer.  
     
     
         11 . The method of  claim 1 , further comprising forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the at least two bumps and the first metal layer, the second metal layer adapted to transfer current from the at least two bumps to the first metal layer, which is adapted to transfer current to the top metal layer of the integrated circuit die.  
     
     
         12 . The method of  claim 11 , wherein the second metal layer is orthogonal to the first metal layer.  
     
     
         13 . The method of  claim 1 , further comprising forming diffusion barriers over and on sides of the first metal layer.  
     
     
         14 . A method comprising: 
 forming a first metal layer over a first barrier seed layer, the first barrier seed layer contacting a top metal layer of an integrated circuit die;    forming a passivation layer over the first metal layer;    forming a polyimide layer over the passivation layer;    developing vias in the polyimide layer;    forming a seed barrier layer in the vias; and    forming first and second bumps over the seed barrier layer.    
     
     
         15 . The method of  claim 14 , wherein the first metal layer is 10-50 μm thick.  
     
     
         16 . The method of  claim 14 , further comprising: 
 forming a dielectric layer over a passivation layer over the top metal layer of the integrated circuit die;    developing vias in the dielectric layer; and    forming the first barrier seed layer in the vias and over the dielectric layer.