Nonplanar device with thinned lower body portion and method of fabrication

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

1 . A semiconductor device comprising: 
 a semiconductor body formed on an insulating layer of a substrate, said semiconductor body having a top surface opposite a bottom surface formed on said insulating layer and a pair of laterally opposite sidewalls wherein the distance between said laterally opposite sidewalls at said top surface is greater than at said bottom surface;    a gate dielectric layer formed on said top surface of said semiconductor body and on said sidewalls of said semiconductor body;    a gate electrode formed on said gate dielectric layer on said top surface and sidewalls of said semiconductor body; and    a pair of source/drain region formed in said semiconductor body on opposite sides of said gate electrode.    
     
     
         2 . The semiconductor device of  claim 1  wherein said distance between said sidewalls at the bottom surface of said semiconductor body is approximately ½ to ⅔ of the distance between the sidewall on top surface of said semiconductor body.  
     
     
         3 . The semiconductor device of  claim 1  wherein the distance between said sidewalls of said semiconductor body become smaller than at the top surface at approximately the mid portion of said semiconductor body.  
     
     
         4 . The semiconductor device of  claim 1  wherein the distance between said sidewalls is uniform at the top portion of said semiconductor body and becomes increasingly smaller towards the bottom portion of said semiconductor body.  
     
     
         5 . The semiconductor device of  claim 1  wherein the distance between said sidewall at the bottom portion of said semiconductor body is made sufficiently small so as to improve the short channel effects of said transistor.  
     
     
         6 . The semiconductor device of  claim 1  wherein the distance between said laterally opposite sidewalls at said top surface of said semiconductor body is approximately 30-20 nm.  
     
     
         7 . The semiconductor device of  claim 1  wherein the distance between said laterally opposite sidewalls near at said bottom portion of said semiconductor body is approximately 15-10 nm.  
     
     
         8 . A semiconductor device comprising: 
 a semiconductor body formed on an insulating layer of a substrate, said semiconductor body having a top surface opposite a bottom surface formed on said insulating layer, and a pair of laterally opposite sidewalls wherein said laterally opposite sidewalls have a facet such that the bottom portion of said semiconductor body is thinner than the top portion of said semiconductor body;    a gate dielectric layer formed on said top surface said semiconductor body and on said sidewalls of said semiconductor body;    a gate electrode formed on said gate dielectric layer on said sidewalls of said semiconductor body and on said top surface of said semiconductor body; and    a pair of source/drain regions formed in said semiconductor body on opposite sides of said gate electrode.    
     
     
         9 . The semiconductor device of  claim 8  wherein said semiconductor body comprises silicon.  
     
     
         10 . The semiconductor device of  claim 8  wherein the distance between said sidewalls near the bottom surface of said semiconductor body is approximately 50-66% of the distance between said sidewalls at the top of said semiconductor body.  
     
     
         11 . A method of forming a device comprising: 
 forming a semiconductor body on an insulating layer of a substrate, said semiconductor body having a top surface opposite a bottom surface formed on said insulating layer and a pair of laterally opposite sidewalls wherein the distance between said laterally opposite sidewalls is less at the bottom surface of said semiconductor body than at the top surface of said semiconductor body;    forming a gate dielectric layer on said top surface of said semiconductor body and on said sidewalls of said semiconductor body;    forming a gate electrode on said gate dielectric layer on said top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body; and    forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.    
     
     
         12 . The method of  claim 11  wherein the width at the bottom of said semiconductor body is approximately ½ to ⅔ of the width at the top of said semiconductor body.  
     
     
         13 . The method of  claim 11  wherein said distance between said sidewalls is uniform at the top portion of said semiconductor body and becomes increasingly smaller near the bottom portion of said semiconductor body.  
     
     
         14 . The method of  claim 11  wherein the distance between said sidewalls of said semiconductor body at the top surface is between 20-30 nm and wherein the distance between said laterally opposite sidewalls near the bottom is between 10-15 nm.  
     
     
         15 . A method of forming a transistor comprising: 
 providing a substrate having an oxide insulating layer formed thereon and a semiconductor thin film formed on the oxide insulating layer;    etching said semiconductor film to form a semiconductor body having a top surface opposite a bottom surface on said oxide insulating film and a pair laterally opposite sidewalls;    etching said semiconductor body to reduce the distance between laterally opposite sidewalls near the bottom of said semiconductor body relative to the top of said semiconductor body;    forming a gate dielectric layer on the top surface and sidewalls of said semiconductor body;    forming a gate electrode on said gate dielectric layer on the top of said semiconductor body and adjacent to the gate dielectric layer on the sidewalls of said semiconductor body; and    forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.    
     
     
         16 . The method of  claim 15  wherein said etching of said semiconductor film stops on said oxide insulating layer.  
     
     
         17 . The method of  claim 15  wherein said semiconductor body comprises silicon and wherein said etching of said semiconductor film is a dry etching process which utilizes a chemistry comprising HBr/O2.  
     
     
         18 . The method of  claim 15  wherein the etching of said semiconductor body reduces the distance between the laterally opposite sidewalls near the bottom portion of said semiconductor body without significantly etching the top portion of said semiconductor body.  
     
     
         19 . The method of  claim 18  wherein said semiconductor body is silicon and is etched by a dry etching process utilizing a chemistry comprising HBr/O 2 .  
     
     
         20 . The method of  claim 18  wherein the power utilized during said etching of said semiconductor body to reduce the thickness of the bottom portion utilizes an RF bias between 50-70 watts.  
     
     
         21 . The method of  claim 18  wherein the etching process utilized to reduce the distance between the sidewalls on the bottom portion of said semiconductor body utilizes a total HBr/O 2  gas flow between 150-180 mL/min.  
     
     
         22 . The method of  claim 15  further comprising after etching said semiconductor body to reduce the distance between laterally opposite sidewalls of said semiconductor body near the bottom portion, exposing said semiconductor body to a wet chemistry comprising NHyOH.  
     
     
         23 . The method  claim 15  wherein said etching of said semiconductor film to form said body utilizes a first process gas chemistry and a first RF bias and said etching of said semiconductor body to reduce the thickness of said bottom portion utilizes a second process gas and a second RF bias wherein said second RF bias is less than said first RF bias.  
     
     
         24 . The method of  claim 23  wherein said first process gas is the same as said second process gas.  
     
     
         25 . The method of  claim 24  wherein said first and second process gas comprises HBr/Ar/O 2 .