Methods of manufacturing a capacitor including a cavity containing a buried layer

Abstract

Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O 2 ) when initially formed.

1 . A method of manufacturing a capacitor, the method comprising: 
 forming an interlayer dielectric on an integrated circuit substrate;    forming a metal plug in the interlayer dielectric;    forming a lower electrode electrically contacting the metal plug, including forming a conductive layer including a cavity and electrically contacting the metal plug and forming a buried layer in the cavity;    forming a dielectric layer on the lower electrode; and    forming an upper electrode on the dielectric layer.    
     
     
         2 . The method of  claim 1  wherein forming a lower electrode includes forming the buried layer of a material that is etch resistant to etch chemicals used to etch silicon oxide and wherein forming a conductive layer comprises forming a noble metal layer.  
     
     
         3 . The method of  claim 1  wherein forming a lower electrode includes forming the buried layer being capable of absorbing additional oxygen (O 2 ) and wherein forming a conductive layer comprises forming a noble metal layer.  
     
     
         4 . The method of  claim 1  wherein forming the lower electrode comprises: 
 sequentially stacking an etch stopper and a mold oxide layer on the interlayer dielectric in a region where the metal plug is formed;    etching portions of the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed to define a lower electrode region;    depositing a noble metal layer on the mold oxide layer, including defining a cavity region in the lower electrode region;    depositing a buried layer on the noble metal layer in the cavity region in the lower electrode region, the buried layer having a different etch rate than that of the mold oxide layer;    planarizing the buried layer and the noble metal layer until the mold oxide layer is exposed; and    removing the mold oxide layer.    
     
     
         5 . The method of  claim 4  wherein the noble metal layer comprises ruthenium (Ru), platinum (Pt), iridium (fr), osmium (Os), palladium (Pd), tungsten (W) and/or cobalt (Co).  
     
     
         6 . The method of  claim 4  wherein forming the buried layer comprises forming the buried layer from tantalum oxide (TaO), titanium dioxide (TiO 2 ), silicon nitride (SiN) and/or silicon (Si), which lacks oxygen.  
     
     
         7 . The method of  claim 6  wherein forming the buried layer comprises depositing a titanium oxide (TaO) layer in a nitrogen (N 2 ) atmosphere.  
     
     
         8 . The method of  claim 4  further comprising forming an oxygen barrier layer on the noble metal layer before forming the buried layer.  
     
     
         9 . The method of  claim 8  wherein forming the oxygen barrier layer comprises forming the oxygen barrier layer of a material having an oxidative characteristic greater than the oxidative characteristic of the metal plug.  
     
     
         10 . The method of  claim 8  wherein forming the oxygen barrier layer comprises forming the oxygen barrier layer from titanium (Ti), titanium rich titanium nitride (Ti-rich TiN), aluminum (Al), tungsten (W) and/or tantalum nitride (TaN).  
     
     
         11 . The method of  claim 4  wherein removing the mold oxide layer comprises moving the mold oxide layer using etch chemicals used to etch silicon oxide.  
     
     
         12 . The method of  claim 4  further comprising thermally treating the lower electrode before forming the dielectric layer.  
     
     
         13 . The method of  claim 12  wherein thermal treating the lower electrode comprises thermal treating the lower electrode in an inert gas atmosphere at a temperature of from about 400° C. to about 750° C.  
     
     
         14 . The method of  claim 4  wherein forming the dielectric layer comprises: 
 depositing a tantalum oxide (TaO) layer on the lower electrode in an oxygen (O 2 ) atmosphere; and    thermally treating the TaO layer to crystallize a portion of the TaO layer.    
     
     
         15 . The method of  claim 14  wherein thermally treating the TaO layer comprises thermally treating the TaO layer in a nitrogen (N 2 ) atmosphere at a temperature of from about 600° C. to about 700° C.  
     
     
         16 . The method of  claim 1  wherein forming a lower electrode further comprises forming an oxygen barrier layer between the buried layer and the conductive layer.  
     
     
         17 . A method of manufacturing a capacitor, the method comprising: 
 forming an interlayer dielectric on a semiconductor substrate;    forming a metal plug in a predetermined portion of the interlayer dielectric;    forming an etch stopper and a mold oxide layer on the interlayer dielectric;    forming a lower electrode region including etching the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed;    sequentially stacking a noble metal layer, an oxygen barrier layer and a buried layer on the mold oxide layer in the lower electrode region;    filling the lower electrode region by planarizing the buried layer, the oxygen barrier layer and the noble metal layer;    removing the mold oxide layer to define a lower electrode;    forming a dielectric layer on the lower electrode; and    forming an upper electrode on the dielectric layer.    
     
     
         18 . A method of manufacturing a capacitor, the method comprising: 
 forming an interlayer dielectric on a semiconductor substrate;    forming a metal plug in a predetermined portion of the interlayer dielectric;    forming an etch stopper and a mold oxide layer on the interlayer dielectric;    forming a lower electrode region by etching the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed;    sequentially stacking a noble metal layer, an oxygen barrier layer and a buried layer on the mold oxide layer;    filling the lower electrode region by planarizing the buried layer, the oxygen barrier layer and the noble metal layer to define a resultant structure;    thermally treating the resultant structure;    removing the mold oxide layer and the buried layer;    removing the oxygen barrier layer to define a lower electrode;    forming a dielectric layer on the lower electrode; and    forming an upper electrode on the dielectric layer.