Methods of forming a semiconductor device having a metal gate electrode and associated devices

Abstract

Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

1 . A highly integrated semiconductor circuit device with metal gate electrodes and a reduced gate pattern size, comprising: 
 a substrate;    a gate insulation layer disposed over the substrate;    a plurality of spaced apart first gate layer patterns stacked on the gate insulation layer above the substrate;    a plurality of spaced apart barrier metal patterns, a respective one stacked on each of the first gate layer patterns above the gate insulation layer, the barrier metal patterns having at least one upwardly extending sidewall;    a plurality of metal gate patterns, a respective one stacked on each of the barrier metal patterns above the first gate layer pattern, the metal gate patterns having at least one upwardly extending sidewall;    a plurality of capping patterns, a respective one stacked on each of the metal gate patterns above the barrier metal pattern; and    an oxidation barrier layer conformably disposed over the barrier metal pattern sidewalls and the metal gate pattern sidewalls and being substantially absent on sidewalls of the first gate layer patterns and the sidewalls of the capping layer pattern, wherein the device is substantially devoid of an oxide layer extending at a boundary portion located between respective barrier metal patterns and the corresponding first gate layer patterns.    
     
     
         2 . A device according to  claim 1 , wherein the oxidation barrier layer has a thickness of between about 5˜100 Å.  
     
     
         3 . A device according to  claim 1 , wherein the first gate layer patterns comprise gate polysilicon patterns.  
     
     
         4 . A device according to  claim 3 , wherein the barrier metal pattern is directly stacked on the gate polysilcon pattern.  
     
     
         5 . A device according to  claim 4 , wherein the oxidation barrier layer comprises metal.  
     
     
         6 . A device according to  claim 4 , wherein the barrier and/or metal gate patterns comprise tungsten.  
     
     
         7 . A device according to  claim 1 , wherein the barrier metal pattern comprises tungsten nitride (WN) or titanium nitride (TiN).  
     
     
         8 . A semiconductor device with a metal gate electrode, comprising: 
 a semiconductor substrate; and    a metal gate electrode on the substrate, the metal gate electrode comprising a stacked gate pattern comprising a gate polysilicon pattern, a barrier metal pattern on the gate polysilicon pattern, and a metal gate pattern on the barrier metal pattern, wherein the device is substantially devoid of an oxide layer extending at a boundary portion located between the barrier metal pattern and the gate polysilicon pattern.    
     
     
         9 . A device according to  claim 8 , wherein the barrier and/or metal gate patterns comprises tungsten.  
     
     
         10 . A device according to  claim 8 , wherein the barrier metal layer comprises tungsten nitride (WN) or titanium nitride (TiN).  
     
     
         11 . A device according to  claim 8 , further comprising an oxidation barrier layer, wherein the oxidation barrier layer covers substantially only sidewall(s) of the metal gate pattern and the barrier metal pattern.  
     
     
         12 . A device according to  claim 8 , further comprising a capping layer on the metal gate pattern layer, wherein the capping layer is patterned thereby forming a device with the stacked gate pattern that comprises, in serial order, the gate polysilicon pattern, the metal-gate pattern and the capping pattern.  
     
     
         13 . A device according to  claim 11 , further comprising a spacer layer abutting a sidewall of the stacked gate pattern including a sidewall(s) of the polysilicon gate pattern, a sidewall(s) of the oxidation barrier layer that resides over the sidewall(s) of the metal-gate pattern and the barrier metal pattern, and a sidewall(s) of the capping pattern.  
     
     
         14 . A device according to  claim 8 , further comprising an impurity-doped region in the semiconductor substrate at opposing sides of the stacked gate pattern.  
     
     
         15 . A device according to  claim 11 , wherein the oxidation layer comprises aluminum.  
     
     
         16 . A device according to  claim 12 , further comprising an oxidation barrier layer, wherein the oxidation barrier layer covers substantially only sidewall(s) of the metal gate pattern and the barrier metal pattern such that the gate polysilicon pattern and the capping pattern are devoid of the oxidation barrier layer.  
     
     
         17 . A semiconductor device with a metal gate electrode, comprising: 
 a semiconductor substrate;    a metal gate electrode on the substrate, the metal gate electrode comprising a stacked gate pattern comprising a gate polysilicon pattern, a barrier metal pattern on the gate polysilicon pattern, and a metal gate pattern on the barrier metal pattern, and a capping pattern on the metal gate pattern; and    an oxidation barrier layer, wherein the oxidation barrier layer covers substantially only sidewall(s) of the metal gate pattern and the barrier metal pattern such that the gate polysilicon pattern and the capping pattern are devoid of the oxidation barrier layer, wherein the device is substantially devoid of an oxide layer extending at a boundary portion located between the barrier metal pattern and the gate polysilicon pattern.    
     
     
         18 . A device according to  claim 17 , wherein the oxidation barrier layer has a thickness of between about 5˜100 Å.