Semiconductor device and manufacturing method of the same

Abstract

To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

1 . A semiconductor device comprising a plurality of element isolating portions made of an insulating film embedded into a trench on a major surface of a semiconductor substrate, wherein: 
 in a first region where a width of an active region is relatively small, a recess amount of each element isolating portion corresponding thereto is relatively large, whereas in a second region where a width of an active region is relatively large, a recess amount of each element isolating portion corresponding thereto is equal to zero, or relatively small.    
   
   
       2 . A semiconductor device as claimed in  claim 1 , wherein: 
 an oxynitride film is formed along side and bottom surface planes of the embedded insulating film in said trench and interfacing with said silicon substrate.    
   
   
       3 . A semiconductor device as claimed in  claim 1 , wherein: 
 the width of said active region in said first region is smaller than 1 μm, and the width of said active region in said second region is larger than, or equal to 1 μm.    
   
   
       4 . A semiconductor device as claimed in  claim 1 , wherein: 
 the active region in said first region includes a well region in which an insulated gate electrode is formed thereon, said well region having ion implanted source and drain diffusion regions in correspondence to said insulated gate electrode, and    said element isolating portion of said first region is positioned near the source and drain diffusion regions where an impurity concentration is greater than an impurity concentration of said well region thereof.    
   
   
       5 . A semiconductor device as claimed in  claim 4 , wherein: 
 an oxynitride film is formed along side and bottom surface planes of the embedded insulating film in said trench and interfacing with said silicon substrate.    
   
   
       6 . A semiconductor device as claimed in  claim 1 , wherein: 
 said first region includes at least one well region each including one or more of said active region with an insulated gate formed thereon, each said active region containing ion implanted source and drain diffusion regions in correspondence to said insulated gate electrode thereof, and    each said element insulating portion of said first region is positioned near the source and drain diffusion regions where an impurity concentration is greater than an impurity concentration of said well region thereof.    
   
   
       7 . A semiconductor device according to  claim 1 , wherein: 
 a height difference of the recess amount between that of a respective element isolation portion corresponding to said first region and a respective element isolation portion corresponding to said second region is larger than a distance defined from the semiconductor substrate surface to a depth where a doping concentration of an impurity region becomes maximum in the active region of said first region.    
   
   
       8 . A semiconductor device comprising: a memory array constituted by a plurality of memory cells arranged on a semiconductor substrate in a matrix shape; a peripheral circuit region where a circuit element different from said plurality of memory cells is formed; and a plurality of element isolating portions made of an insulating film embedded into a trench on a major surface of a semiconductor substrate, wherein: 
 in said memory array, a recess amount of each element isolating portion corresponding thereto is relatively large, whereas in said peripheral circuit region, a recess amount of each element isolating portion corresponding thereto is equal to zero, or relatively small.    
   
   
       9 . A semiconductor device as claimed in  claim 8 , wherein: 
 an oxynitride film is formed along side and bottom surface planes of the embedded insulating film in said trench and interfacing with said silicon substrate.    
   
   
       10 . A semiconductor device as claimed in  claim 8 , wherein: 
 the width of an active region in said memory array is smaller than 1 μm, and the width of an active region in said peripheral circuit region is larger than, or equal to 1 μm.    
   
   
       11 . A semiconductor device as claimed in  claim 8 , wherein: 
 the recess amount of said element isolating portion in said memory array is approximately 80 nm, whereas the recess amount of said element isolating portion in said peripheral circuit region is approximately 0 to 40 nm.    
   
   
       12 . A semiconductor device as claimed in  claim 8 , wherein: 
 an activated region in said memory array is a stripe shape.    
   
   
       13 . A semiconductor device as claimed in  claim 8 , wherein: 
 said plurality of memory cells constitute memory cells of a flash memory arranged by that source/drain regions of said plurality of memory cells are mutually connected in parallel thereto in each of columns, and a plurality of word lines are elongated in each of rows.    
   
   
       14 . A semiconductor device as claimed in  claim 13 , wherein: 
 each of said plural memory cells is comprised of:    a lower layer conductive film for a floating gate electrode, which is provided via a first insulating film on a channel region between said source/drain regions;    an upper layer conductive film for a floating gate electrode, which is electrically connected to said lower layer conductive film for the floating gate electrode, and is elongated from said lower layer conductive layer for the floating gate electrode via a second insulating film formed on said source/drain region to said source/drain region; and    a conductive film for a control gate electrode, which is provided via a third insulating film on the upper layer conductive film for the floating gate electrode, and is operated as said word line overlapped on said upper layer conductive film for the floating gate.    
   
   
       15 . A semiconductor device according to  claim 14 , wherein: 
 a height difference of the recess amount between that of a respective element isolation portion corresponding to said memory array and a respective element isolation portion corresponding to said peripheral circuit region is larger than a distance defined from the semiconductor substrate surface to a depth where a doping concentration of an impurity region becomes maximum in the active region.    
   
   
       16 . A semiconductor device according to  claim 8 , wherein: 
 said memory array includes at least one well region each including one or more of said active region with an insulated gate formed thereon, each said active region containing ion implanted source and drain diffusion regions in correspondence to said insulated gate electrode thereof, and    each said element insulating portion of said memory array is positioned near the source and drain diffusion regions where an impurity concentration is greater than an impurity concentration of said well region thereof.    
   
   
       17 . A semiconductor device according to  claim 16 , wherein: 
 an oxynitride film is formed along side and bottom surface planes of the embedded insulating film in said trench and interfacing with said silicon substrate.    
   
   
       18 . A semiconductor device according to  claim 16 , wherein: 
 a height difference of the recess amount between that of a respective element isolation portion corresponding to said memory array and a respective element isolation portion corresponding to said peripheral circuit region is larger than a distance defined from the semiconductor substrate surface to a depth where a doping concentration of an impurity region becomes maximum in the active region.    
   
   
       19 . A semiconductor device according to  claim 8 , wherein: 
 a height difference of the recess amount between that of a respective element isolation portion corresponding to said memory array and a respective element isolation portion corresponding to said peripheral circuit region is larger than a distance defined from the semiconductor substrate surface to a depth where a doping concentration of an impurity region becomes maximum in the active region.