Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory

Abstract

A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

1 . An random access memory, comprising: 
 a floating gate formed on a semiconductor substrate;    a dielectric layer formed on said semiconductor substrate to cover sidewalls of said floating gate;    two control gates formed on said dielectric layer and at two sides of said floating gate respectively, wherein the profile of said control gate at one side of said floating gate is an L-like shape; and    two oxide spacers formed on said two control gates respectively.    
   
   
       2 . The random access memory of  claim 1 , wherein the profile of the combination of said control gate and said oxide spacer at one side of said floating gate is substantially rectangular.  
   
   
       3 . The random access memory of  claim 1 , wherein the control gate is a polysilicon layer, and the oxide spacer is a polyoxide layer.  
   
   
       4 . The conductive spacer process of  claim 1 , further comprising forming a borderless contact on said sidewall control gate.  
   
   
       5 . The conductive spacer process of  claim 1 , further comprising forming a borderless contact on said sidewall control gate.