Single-poly non-volatile memory device and its operation method

Abstract

A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the ONO sidewall.

1 . A method for programming a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the P+ drain doping region to a bias drain voltage VD being negative with respect to the N well voltage V NW ;    floating the P+ source doping region; and    connecting the control gate to a bias gate voltage VG being equal to or positive with respect to the N well voltage V NW  such that the first channel is turned off and that electron-hole pairs is generated at a junction between the N-type well and the P-type drain doping region to induce Band-to-Band Hot Electron Injection (BBHE) into the charge trapping medium.    
   
   
       2 . The method according to  claim 1  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       3 . The method according to  claim 2  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       4 . The method according to  claim 1  wherein the control gate comprises doped polysilicon.  
   
   
       5 . The method according to  claim 1  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       6 . The method according to  claim 1  wherein the drain voltage V D =−3V˜−5V.  
   
   
       7 . The method according to  claim 1  wherein the gate voltage V G =0V˜2V.  
   
   
       8 . The method according to  claim 1  wherein the N well is grounded.  
   
   
       9 . A method for programming a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the P+ drain doping region to a bias drain voltage V D  being negative with respect to the N well voltage V NW ;    connecting the P+ source doping region to a source voltage V S ; and    connecting the control gate to a bias gate voltage V G  being negative with respect to the N well voltage V NW  such that the first channel is turned on to trigger channel hot hole induced hot electron (CHHIHE) injection into the charge trapping medium.    
   
   
       10 . The method according to  claim 9  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       11 . The method according to  claim 10  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       12 . The method according to  claim 9  wherein the control gate comprises doped polysilicon.  
   
   
       13 . The method according to  claim 9  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       14 . The method according to  claim 9  wherein the drain voltage V D =−3V˜−5V.  
   
   
       15 . The method according to  claim 9  wherein the gate voltage V G =−0.5V˜−2V.  
   
   
       16 . The method according to  claim 9  wherein the source voltage V S =0V.  
   
   
       17 . The method according to  claim 9  wherein the N well is grounded.  
   
   
       18 . A method for reading a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region comprising a first channel region, a second channel region between the first channel region and the P+ drain doping region, and a third channel between the first channel and the P+ source doping region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the P+ drain doping region to a drain voltage V D ;    connecting the P+ source doping region to a bias source voltage V S  being negative with respect to the N well voltage VNW to form a depletion region between the P+ source doping region and the N well; and    connecting the control gate to a bias gate voltage V G  being negative with respect to the N well voltage V NW  such that the first channel is turned on.    
   
   
       19 . The method according to  claim 18  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       20 . The method according to  claim 18  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       21 . The method according to  claim 18  wherein the control gate comprises doped polysilicon.  
   
   
       22 . The method according to  claim 18  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       23 . The method according to  claim 18  wherein the source voltage V S =−1.2V˜−3.3V.  
   
   
       24 . The method according to  claim 18  wherein the gate voltage V G =−1V˜−3.3V.  
   
   
       25 . The method according to  claim 18  wherein the N well is grounded.  
   
   
       26 . The method according to  claim 18  wherein the drain voltage V D =0V.  
   
   
       27 . The method according to  claim 18  wherein the depletion region renders the channel between the P+ source and gate electrode conductive and is connected to the turned on first channel.