Method of forming via recess in underlying conductive line

Abstract

A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

1 . A method of fabricating a semiconductor device comprising: 
 forming a via in a dielectric layer and opening to a conductive line underlying the dielectric layer; and    forming a via recess in the conductive line at the via, the via recess in the conductive line having a depth ranging from about 100 angstroms to about 600 angstroms.    
   
   
       2 . The method of  claim 1 , wherein the conductive line comprises a material selected from the group consisting of metal alloy, copper, aluminum, copper alloy, poly-crystalline silicon, metal silicide, compounds thereof, composites thereof, and combinations thereof.  
   
   
       3 . The method of  claim 1 , further comprising: 
 filling the via recess and at least partially filling the via with a via-fill material.    
   
   
       4 . The method of  claim 3 , wherein the via-fill material comprises: 
 a barrier layer at least partially lining interior surfaces of the via recess and at least partially lining interior surfaces of the via; and    a conducting material, wherein the barrier layer is located between at least part of the conducting material and at least part of the dielectric layer.    
   
   
       5 . The method of  claim 4 , wherein the conducting material is electrically connected to the conductive line through the barrier layer.  
   
   
       6 . The method of  claim 4 , wherein the barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, tungsten, compounds thereof, composites thereof, and combinations thereof.  
   
   
       7 . The method of  claim 4 , wherein the conducting material comprises material selected from a group consisting of metal alloy, copper, copper alloy, aluminum, aluminum alloy, tungsten, poly-crystalline silicon, compounds thereof, composites thereof, and combinations thereof.  
   
   
       8 . The method of  claim 1 , wherein the dielectric layer comprises: 
 a capped layer; and    a layer of insulating material overlying the capped layer.    
   
   
       9 . The method of  claim 8 , wherein the capped layer is a material comprising silicon-carbon having a thickness less than about 600 angstroms.  
   
   
       10 . The method of  claim 9 , wherein the capped layer has at least 30% carbon.  
   
   
       11 . The method of  claim 1 , wherein the size of the via is less than about 900 angstroms.  
   
   
       12 . The method of  claim 1 , wherein the forming of the via recess includes a pre-metal cleaning process performed after the forming of the via.  
   
   
       13 . The method of  claim 12 , wherein the pre-metal cleaning is a process selected from the group consisting of an argon sputter, an ammonia-based reactive process, a hydrogen-based reactive process, and combinations thereof.  
   
   
       14 . The method of  claim 1 , wherein the depth of the via recess formed in the conductive line is between about 150 angstroms and about 300 angstroms.  
   
   
       15 . The method of  claim 1 , wherein the depth of the via recess formed in the conductive line is between about 300 angstroms and about 600 angstroms.  
   
   
       16 . The method of  claim 1 , wherein the dielectric layer has a dual damascene structure comprising another conductive line formed therein and being electrically connected to the conducting material in the via.  
   
   
       17 . A method of fabricating a semiconductor device comprising: 
 forming a dielectric layer comprising an insulating material layer and a capped layer, wherein the capped layer has a dielectric constant less than about 4;    forming a via in the dielectric layer and opening to a conductive line underlying the dielectric layer;    forming a via recess in the conductive line at the via, the via recess in the conductive line having a depth ranging from about 100 angstroms to about 600 angstroms; and    filling the via recess and at least partially filling the via with a via-fill material, such that the via-fill material is electrically connected to the conductive line.    
   
   
       18 . The method of  claim 17 , wherein the depth of the via recess formed in the conductive line is between about 150 angstroms and 300 angstroms.  
   
   
       19 . The method of  claim 17 , wherein the depth of the via recess formed in the conductive line is between about 300 angstroms and 600 angstroms.  
   
   
       20 . A method of fabricating a semiconductor device comprising: 
 forming a dielectric layer comprising an insulating material layer and a capped layer, 
 wherein the capped layer is located between the insulating material layer and a conductive line underlying the dielectric layer,  
 wherein the capped layer has a dielectric constant less than about 4,  
 wherein the capped layer comprises silicon carbon, and  
 wherein the capped layer comprises at least 30% carbon;  
   forming a via in the dielectric layer and opening to the conductive line;    forming a via recess in the conductive line at the via, the via recess in the conductive line having a depth ranging from about 100 angstroms to about 600 angstroms; and    filling the via recess and at least partially filling the via with a via-fill material, such that the via-fill material is electrically connected to the conductive line.