Hardmask for improved reliability of silicon based dielectrics

Abstract

The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

1 . A semiconductor structure comprising: 
 a low k dielectric material having a dielectric constant of about 3.0 or less located on a surface of a substrate; and    a hardmask located on said low k dielectric material, said hardmask comprising a lower region of a hermetic oxide material and an upper region comprising atoms of Si, C and H located above said hermetic oxide material wherein said lower region of said hardmask has a C content of less than about 5 atomic % and said upper region of said hardmask has a C content from about 10 to about 80 atomic %.    
   
   
       2 . The semiconductor structure of  claim 1  wherein the hermetic oxide material of said hardmask has a density of between 1.2 gm/cm 3  and 2.3 gm/cm 3 .  
   
   
       3 . The semiconductor structure of  claim 1  wherein said lower region of said hardmask has a thickness from about 0.5 to about 10 nm.  
   
   
       4 . The semiconductor structure of  claim 1  wherein said upper region has a thickness from about 5 to about 100 nm.  
   
   
       5 . The semiconductor structure of  claim 1  wherein said low k dielectric material has a first atomic concentration of C ranging between about 5 atomic % to about 45 atomic % and said first atomic concentration of C in said low k dielectric material is greater than said C content in said lower region of said hardmask.  
   
   
       6 . The semiconductor structure of  claim 1  wherein said upper region of said hardmask further comprises atoms of O, atoms of N or a combination of atoms of O and N.  
   
   
       7 . The semiconductor structure of  claim 1  wherein said low k dielectric material comprises a SiCOH dielectric or a thermosetting polyarylene ether.  
   
   
       8 . The semiconductor structure of  claim 1  wherein said low k dielectric material is porous.  
   
   
       9 . The semiconductor structure of  claim 1  wherein said hardmask has a graded C content that is low at an interface with said low k dielectric material and increases with distance from said interface.  
   
   
       10 . A hardmask comprising a lower region of a hermetic oxide material and an upper region comprising atoms of Si, C and H located above said hermetic oxide material, wherein said lower region of said hardmask prevents the penetration of air and moisture through the hardmask and has a C content of less than about 5 atomic % and said upper region of said hardmask has a C content from about 10 to about 80 atomic.  
   
   
       11 . The hardmask of  claim 10  wherein said C content is lower in said lower region than in said upper region.  
   
   
       12 . The hardmask of  claim 10  wherein the hermetic oxide material has a density of between 1.2 g/cm 3  and 2.3 g/cm 3 .  
   
   
       13 . The hardmask of  claim 10  wherein said lower region has a thickness from about 0.5 to about 10 nm, and said upper region has a thickness from about 5 to about 100 nm.