Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Abstract

After formation of Cu interconnections 46 a to 46 e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46 a to 46 e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

1 - 20 . (canceled) 
   
   
       21 . A method of manufacturing a semiconductor device, the method comprising:
 (a) forming an interlayer dielectric film over a major surface of a wafer, the interlayer dielectric film including an upper silicon oxide layer and a lower silicon oxide layer of a low dielectric constant which is smaller than a dielectric constant of said upper silicon oxide layer said upper silicon oxide layer being formed directly on said lower silicon oxide layer;   (b) forming a through-hole in the interlayer dielectric film and forming a groove in the interlayer dielectric film so as to reach an inner region of the lower silicon oxide layer through the upper silicon oxide layer, and such that a portion of the through-hole is at the bottom of the groove;   (c) forming a barrier metal film over the interlayer dielectric film including the groove and the through-hole   (d) forming a copper (Cu) or Cu alloy layer over the barrier metal film;   (e) removing the barrier metal film and the Cu or Cu alloy layer outside the groove and the through-hole, such that a surface of the upper silicon oxide layer is exposed;   (f) treating a surface of the Cu or Cu alloy layer and the exposed surface of the upper silicon oxide layer with an ammonia plasma; and   (g) forming an insulating Cu diffusion barrier layer on the treated surfaces by plasma CVD.   
   
   
       22 . The method according to  claim 21 , comprising depositing the insulating Cu diffusion barrier layer directly on the treated surface. 
   
   
       23 . The method according to  claim 21 , comprising forming the insulating Cu diffusion barrier by depositing a layer comprising silicon nitride. 
   
   
       24 . The method according to  claim 21 , comprising forming the Cu or Cu alloy layer by:
 depositing a seed layer; and   electroplating or electroless plating the Cu or Cu alloy on the seed layer.   
   
   
       25 . The method according to  claim 21 , comprising treating the surface of the Cu or Cu alloy layer with the ammonia plasma at:
 an ammonia flow rate of not less than 20 sccm;   a pressure of 0.5 to 6 Torr;   a temperature not higher than 450° C. and;   a RF power of not less than 300 watts.   
   
   
       26 . The method according to  claim 25 , comprising treating the surface of the Cu or Cu alloy layer with the ammonia plasma for not longer than 180 seconds. 
   
   
       27 . The method according to  claim 23 , comprising treating the surface of the Cu or Cu alloy layer with the ammonia plasma and depositing the silicon nitride diffusion barrier layer in the same tool. 
   
   
       28 . The method according the  claim 22 , wherein portions of the Cu or Cu alloy layer are removed by chemical mechanical polishing to leave an exposed oxidized surface, and wherein the step (f) includes treating the exposed oxidized surface with the ammonia plasma to substantially reduce the oxidized surface. 
   
   
       29 . The method according to  claim 21 , wherein a specific dielectric constant of the lower silicon oxide layer is lower than 3.0 
   
   
       30 . The method according to  claim 21 , wherein the lower silicon oxide layer comprises a film selected from the group consisting of an inorganic SOG film formed using hydrogen silsesquioxane as a raw material, an organic SOG film formed using tetra alkoxy silane and alkyl alkoxy silane as a raw material, and a fluorocarbon polymer film formed by plasma CVD, and
 wherein the upper silicon oxide layer comprises a TEOS oxide film formed by plasma CVD by using TEOS as a raw material.   
   
   
       31 . A method of manufacturing a semiconductor device, the method comprising:
 (a) forming a first insulating film over a semiconductor substrate;   (b) forming a first interconnection in the first insulating film;   (c) forming a second insulating film over the first insulating film and the first interconnection;   (d) forming a through-hole in the second insulating film, the through-hole extending to the first interconnection;   (e) forming a groove in the second insulating film, the groove being open to the first interconnection via the through-hole;   (f) forming a barrier metal film over the second insulating film including the groove and the through-hole;   (g) after the step (f), forming a conductive film containing copper over the barrier metal film;   (h) after the step (g), removing the barrier metal film and the conductive film outside the groove and the through-hole, such that a surface of the second insulating film is exposed;   (i) after the step (h), treating a surface of the conductive film and a surface of the second insulating film with an ammonia plasma; and   (j) after the step (i), forming a third insulating film over the conductive film and the second insulating film.   
   
   
       32 . The method according to  claim 31 ,
 wherein the second insulating film includes an upper layer and a lower layer, and   wherein a dielectric constant of the lower layer is smaller than that of the upper layer.   
   
   
       33 . The method according to  claim 32 ,
 wherein the dielectric constant of the lower layer is smaller than 3.0.   
   
   
       34 . The method according to  claim 32 ,
 wherein the upper layer is formed of a silicon oxide film.   
   
   
       35 . The method according to  claim 32 ,
 wherein the lower layer is formed of an organic film.   
   
   
       36 . The method according to  claim 31 ,
 wherein the third insulating film contains silicon and nitrogen.   
   
   
       37 . The method according to  claim 31 ,
 wherein the step (g) comprises:   (g1) depositing a copper seed layer on the barrier metal film; and   (g2) electroplating or electroless plating the conductive film containing copper on the copper seed layer.   
   
   
       38 . The method according to  claim 31 ,
 wherein, in the step (i), the ammonia plasma is performed at condition of:   an ammonia flow rate of not less than 20 sccm;   a pressure of 0.5 to 6 Torr;   a temperature not higher than 450□; and   a RF power of not less than 300 watts.   
   
   
       39 . The method according to  claim 38 ,
 wherein, in the step (i), the ammonia plasma treatment is performed for not longer than 180 seconds.   
   
   
       40 . The method according to  claim 31 ,
 wherein the steps (i) and (j) are performed in the same tool.   
   
   
       41 . The method according to  claim 31 ,
 wherein the barrier metal film contains tantalum.