Symmetric capacitor structure

Abstract

A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

1 . A structure, comprising:
 a first doped region formed within a substrate, wherein said first doped region comprises a first dopant having a first polarity;   a second doped region formed within said substrate and over said first doped region, wherein said second doped region forms a first electrode of a symmetric capacitor;   a third doped region formed within said substrate and over first doped region, wherein said third doped region forms a second electrode of said symmetric capacitor, wherein each of said second doped region and said third doped region comprises a same second dopant having a second polarity, wherein each of said second doped region and said third doped region is formed simultaneously, and wherein said first doped region, said second doped region, and said third doped region in combination form a PN junction; and   a first shallow trench isolation structure formed between said second doped region and said third doped region, wherein said first shallow trench isolation structure electrically isolates said second doped region from said third doped region, wherein said symmetric capacitor comprises a main capacitance, wherein said structure comprises a first parasitic capacitance and a second parasitic capacitance, wherein said main capacitance comprises a capacitance between said second doped region and said third doped region, wherein said first parasitic capacitance represents a parasitic connection between said second doped region and said first doped region, wherein said second parasitic capacitance represents a parasitic connection between said third doped region and said first doped region, wherein a first distance between said second doped region and said first doped region is about equal to a second distance between said third doped region and said first doped region, and wherein said first parasitic capacitance is about equal to said second parasitic capacitance.   
   
   
       2 . The structure of  claim 1 , further comprising:
 a fourth doped region formed within said substrate and over first doped region, wherein said fourth doped region comprises said first dopant;   a fifth doped region formed within said substrate and over first doped region, wherein said fifth doped region comprises said first dopant;   a second shallow trench isolation structure formed between said second doped region and said fourth doped region, wherein said second shallow trench isolation structure electrically isolates said second doped region from said fourth doped region;   a third shallow trench isolation structure formed between said third doped region and said fifth doped region, wherein said third shallow trench isolation structure electrically isolates said third doped region from said fifth doped region, wherein said fourth doped region and said fifth doped region is biased electrically such that said PN junction is reverse biased, and wherein said symmetric capacitor is electrically isolated from said substrate.   
   
   
       3 . The structure of  claim 2 , wherein said first doped region is electrically connected to said fourth doped region and said fifth doped region, and wherein a voltage is electrically connected to said first doped region voltage through said fourth doped region and said fifth doped region. 
   
   
       4 . The structure of  claim 2 , wherein said first polarity comprises an opposite polarity as said second polarity. 
   
   
       5 . The structure of  claim 2 , wherein each of said first shallow trench isolation structure, said second shallow trench isolation structure, and said third shallow trench isolation structure comprises a material selected from the group consisting of an oxide material and a high-K dielectric material. 
   
   
       6 . The structure of  claim 2 , further comprising:
 a first electrical contact formed over said second doped region;   a second electrical contact formed over said third doped region;   a first metal wire formed over and in electrical contact with said first electrical contact;   a second metal wire formed over and in electrical contact with said second electrical contact;   a first electrically conductive via formed over and in electrical contact with said first metal wire;   a second electrically conductive via formed over and in electrical contact with said second metal wire;   a third metal wire formed over and in electrical contact with said first electrically conductive via; and   a fourth metal wire formed over and in electrical contact with said second electrically conductive via.   
   
   
       7 . The structure of  claim 6 , wherein said first electrical contact is electrically connected said second doped region, and wherein second electrical contact is electrically connected to said third doped region. 
   
   
       8 . The structure of  claim 6 , further comprising:
 a first layer of gate oxide formed over said second doped region;   a first poly-silicon gate formed over said first layer of gate oxide such that said first poly-silicon gate is located between said first layer of gate oxide and said first electrical contact;   a second layer of gate oxide formed over said third doped region; and   a second poly-silicon gate formed over said second layer of gate oxide such that said second poly-silicon gate is located between said second layer of gate oxide and said second electrical contact.   
   
   
       9 . The structure of  claim 6 , further comprising:
 a dielectric formed over said substrate and surrounding said first electrical contact, said second electrical contact, said first metal wire, said second metal wire, said first electrically conductive via, second electrically conductive via, said third metal wire, and said fourth metal wire.   
   
   
       10 . The structure of  claim 1  wherein, said substrate comprises a material selected from the group consisting of silicon, Silicon on insulator, GaAs, and InP.