Single-gate non-volatile memory and operation method thereof

Abstract

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

1 . A single-gate non-volatile memory, comprising:
 a semiconductor substrate;   a transistor, having a first dielectric layer, a first electrically-conductive gate and a plurality of first ion-doped regions, said first dielectric layer disposed on the surface of said semiconductor substrate, said first electrically-conductive gate stacked on said first dielectric layer, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain; and   a capacitor structure having a second dielectric layer, a second electrically-conductive gate and a second ion-doped region, said second dielectric layer disposed on the surface of said semiconductor substrate said second electrically-conductive gate, stacked on said second dielectric layer, said second ion-doped region disposed at one side of said second dielectric layer; wherein said first electrically-conductive gate and said second electrically-conductive gate being separated and electrically interconnected to form a single floating gate.   
   
   
       2 . The memory of  claim 1 , wherein said semiconductor substrate is a P-type semiconductor substrate or an N-type semiconductor substrate. 
   
   
       3 . The memory of  claim 1 , wherein said first ion-doped regions and said second ion-doped region are doped with a first type ion, which said semiconductor substrate is doped with a second type ion, and said first type ion is different from said second type ion. 
   
   
       4 . The memory of  claim 3 , wherein said semiconductor substrate is a P-type semiconductor substrate, and said first ion-doped regions and said second ion-doped region are N-type ion-doped regions. 
   
   
       5 . The memory of  claim 3 , wherein said semiconductor substrate is an N-type semiconductor substrate, and said first ion-doped regions and said second ion-doped region are P-type ion-doped regions. 
   
   
       6 . The memory of  claim 1 , further comprising a third ion-doped region, which is embedded inside said semiconductor substrate and is disposed below said first ion-doped regions, wherein said third ion-doped region is doped with the same type ion as said second ion-doped region. 
   
   
       7 . The memory of  claim 6 , wherein said third ion-doped region extends to a region below said second ion-doped region. 
   
   
       8 . The memory of  claim 7 , further comprising an isolation well, which is embedded inside said semiconductor substrate and is disposed below said third ion-doped region, wherein said isolation well and said second ion-doped region are doped with a first type ion, and said third ion-doped region and said semiconductor substrate are doped with a second type ion, which said first type ion is different from said second type ion. 
   
   
       9 . The memory of  claim 6 , wherein said semiconductor substrate is an N-type semiconductor substrate, and said second ion-doped region and said third ion-doped region are P-type ion-doped regions. 
   
   
       10 . The memory of  claim 6 , wherein said semiconductor substrate is a P-type semiconductor substrate, and said second ion-doped region and said third ion-doped region are N-type ion-doped regions.