Low fabrication cost, fine pitch and high reliability solder bump

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

What is claimed is: 
     
         1 . A process for fabricating a chip, comprising:
 providing a silicon substrate, multiple layers of interconnecting lines, multiple insulating layers, wherein said multiple insulating layers comprise an oxide material, multiple metal vias in said multiple insulating layers and between said multiple layers of interconnecting lines, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and a polymer layer over said silicon substrate, wherein an opening in said polymer layer is over a contact point of said multiple layers of interconnecting lines and exposes said contact point, and wherein said polymer layer is formed by a process comprising coating a photosensitive material; and   forming a metal bump on said contact point and on said polymer layer, wherein said forming said metal bump comprises forming a metal layer on said contact point, on said polymer layer and in said opening in said polymer layer, wherein said metal layer comprises a barrier layer on said contact point, on said polymer layer and in said opening in said polymer layer, and a seed layer formed after said barrier layer is formed, followed by forming a photoresist layer on said metal layer, wherein an opening in said photoresist layer is over said metal layer and exposes said metal layer, followed by electroplating a copper pillar on said metal layer exposed by said opening in said photoresist layer, wherein said copper pillar has a thickness between 10 micrometers and 100 micrometers, followed by removing said photoresist layer, followed by reducing a transverse dimension of said copper pillar by a process comprising a wet etching process, followed by removing said barrier layer not under said copper pillar by a process comprising an anisotropic etching process.   
     
     
         2 . The process of  claim 1 , wherein said barrier layer comprises titanium. 
     
     
         3 . The process of  claim 1 , wherein said seed layer is formed using a sputter chamber and using a copper source. 
     
     
         4 . The process of  claim 1 , wherein said barrier layer comprises titanium nitride. 
     
     
         5 . The process of  claim 1 , after said electroplating said copper pillar, further comprising electroplating a nickel layer on said copper pillar in said opening in said photoresist layer, followed by said removing said photoresist layer. 
     
     
         6 . The process of  claim 5 , wherein said nickel layer has a thickness between 1 and 10 micrometers. 
     
     
         7 . The process of  claim 1 , after said electroplating said copper pillar, further comprising electroplating a solder over said copper pillar in said opening in said photoresist layer, followed by said removing said photoresist layer. 
     
     
         8 . The process of  claim 7 , wherein said solder has a thickness between 30 and 100 micrometers. 
     
     
         9 . The process of  claim 1 , wherein said polymer layer comprises polyimide. 
     
     
         10 . The process of  claim 1 , wherein said multiple layers of interconnecting lines comprise copper. 
     
     
         11 . The process of  claim 1 , after said removing said barrier layer, further comprising reflowing said solder. 
     
     
         12 . A process for fabricating a chip, comprising:
 providing a silicon substrate, multiple layers of interconnecting lines, multiple insulating layers, wherein said multiple insulating layers comprise an oxide material, multiple metal vias in said multiple insulating layers and between said multiple layers of interconnecting lines, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and a polymer layer over said silicon substrate, wherein an opening in said polymer layer is over a contact point of said multiple layers of interconnecting lines and exposes said contact point, and wherein said polymer layer is formed by a process comprising coating a photosensitive material; and   forming a metal bump on said contact point and on said polymer layer, wherein said forming said metal bump comprises forming a metal layer on said contact point, on said polymer layer and in said opening in said polymer layer, wherein said metal layer comprises a barrier layer sputtered on said contact point, on said polymer layer and in said opening in said polymer layer, and a seed layer formed using a sputter chamber and a copper source after said barrier layer is sputtered, followed by forming a photoresist layer on said metal layer, wherein an opening in said photoresist layer is over said metal layer and exposes said metal layer, followed by electroplating a copper pillar on said metal layer exposed by said opening in said photoresist layer, wherein said copper pillar has a thickness between 10 micrometers and 100 micrometers, followed by electroplating a nickel layer over said copper pillar, followed by electroplating a solder over said nickel layer, followed by removing said photoresist layer, followed by reducing a transverse dimension of said copper pillar by a process comprising a wet etching process, followed by removing said barrier layer not under said copper pillar by a process comprising an anisotropic etching process.   
     
     
         13 . The process of  claim 12 , wherein said barrier layer comprises titanium. 
     
     
         14 . The process of  claim 12 , wherein said barrier layer comprises titanium nitride. 
     
     
         15 . The process of  claim 12 , wherein said multiple layers of interconnecting lines comprises aluminum. 
     
     
         16 . The process of  claim 12 , wherein said nickel layer has a thickness between 1 and 10 micrometers. 
     
     
         17 . The process of  claim 12 , wherein said solder has a thickness between 30 and 100 micrometers. 
     
     
         18 . The process of  claim 12 , wherein said polymer layer comprises polyimide. 
     
     
         19 . The process of  claim 12 , wherein said multiple layers of interconnecting lines comprises copper. 
     
     
         20 . The process of  claim 12 , after said removing said barrier layer, further comprising reflowing said solder.