CMOS devices with schottky source and drain regions

Abstract

A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.

1 . A semiconductor structure comprising:
 a semiconductor substrate;   an NMOS device at a surface of the semiconductor substrate, the NMOS device comprising a Schottky source/drain extension region; and   a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials.   
   
   
       2 . The semiconductor structure of  claim 1 , wherein the Schottky source/drain extension region comprises a metal silicide. 
   
   
       3 . The semiconductor structure of  claim 1 , wherein the NMOS device further comprises a first gate stack on the semiconductor substrate and a first gate spacer on a sidewall of the first gate stack, and the PMOS device further comprises a second gate stack on the semiconductor substrate and a second gate spacer on a sidewall of the second gate stack, and wherein the second gate spacer is thicker than the first gate spacer. 
   
   
       4 . The semiconductor structure of  claim 3  further comprising a tensile contact etch stop layer extending from over the NMOS device to over the PMOS device. 
   
   
       5 . The semiconductor structure of  claim 3 , wherein the Schottky source/drain extension region has an inner edge substantially aligned to a sidewall of the first gate spacer. 
   
   
       6 . The semiconductor structure of  claim 1 , wherein the PMOS device further comprises a source/drain region adjoining the source/drain extension region, and a source/drain silicide region on the source/drain region, and wherein the source/drain silicide region and the Schottky source/drain extension region of the NMOS device comprise same metals. 
   
   
       7 . The semiconductor structure of  claim 1 , wherein a metal in the Schottky source/drain extension region has a work function close to a conduction band of the semiconductor substrate. 
   
   
       8 . A semiconductor structure comprising:
 a semiconductor substrate;   an NMOS device at a surface of the semiconductor substrate, the NMOS device comprising:
 a first gate dielectric on the semiconductor substrate; 
 a first gate electrode on the first gate dielectric; 
 a first gate spacer on a sidewall of the first gate electrode and a sidewall of the first gate dielectric; and 
 a first source/drain extension region having a inner edge substantially aligned to an outer edge of the first gate spacer, wherein the first source/drain extension region is a metal silicide region having a Schottky contact with the semiconductor substrate; and 
   a PMOS device at the surface of the semiconductor substrate, the PMOS device comprising:
 a second gate dielectric on the semiconductor substrate; 
 a second gate electrode on the second gate dielectric; 
 a second gate spacer on a sidewall of the second gate electrode and a sidewall of the second gate dielectric, wherein the second gate spacer is thicker than the first gate spacer; 
 a second source/drain extension region having an inner edge substantially aligned to an edge of the first gate stack, wherein the second source/drain extension region has an Ohmic contact with the semiconductor substrate; 
 a source/drain region adjacent the second gate stack, wherein the source/drain region is substantially aligned to an outer edge of the second gate spacer; and 
 a silicide region on the second source/drain region, wherein the first source/drain extension region and the silicide region comprise same metals. 
   
   
   
       9 . The semiconductor structure of  claim 8  further comprising a contact etch stop layer having a tensile stress extending from over the NMOS device to over the PMOS device. 
   
   
       10 . The semiconductor structure of  claim 8 , wherein the first source/drain extension region comprises a metal having a work function of lower than about 4.25 eV. 
   
   
       11 . A semiconductor structure comprising:
 a semiconductor substrate;   an NMOS region in the semiconductor substrate, wherein the NMOS region only comprises a base semiconductor substrate having a first valence band;   a PMOS region in the semiconductor substrate, wherein the PMOS region comprises an additional semiconductor layer on the base semiconductor substrate, and wherein the additional semiconductor layer has a second valence band lower than the first valence band;   an NMOS device in the NMOS region, the NMOS device comprising:
 a first gate stack on the base semiconductor substrate; 
 a first Schottky source/drain extension region adjacent the first gate stack; and 
   a PMOS device in the PMOS region, the PMOS device comprising:
 a second gate stack over the additional semiconductor layer; 
 a second Schottky source/drain extension region adjacent the second gate stack, wherein the second Schottky source/drain extension region has a bottom surface lower than a top surface of the additional semiconductor layer, and wherein the first and the second Schottky source/drain extension regions comprise same metals. 
   
   
   
       12 . The semiconductor structure of  claim 11 , wherein the first Schottky source/drain extension region comprises a silicide, and the second Schottky source/drain extension region comprises a germano-silicide. 
   
   
       13 . The semiconductor structure of  claim 11 , wherein the bottom surface of the second Schottky source/drain extension region is between the top surface and a bottom surface of the additional semiconductor layer. 
   
   
       14 . The semiconductor structure of  claim 11 , wherein the bottom surface of the second Schottky source/drain extension region is level with or lower than a bottom surface of the additional semiconductor layer. 
   
   
       15 . The semiconductor structure of  claim 11 , wherein the base semiconductor substrate is a silicon substrate, the additional semiconductor layer is a silicon-germanium layer, and wherein the second Schottky source/drain extension region comprises a metal silicide layer on a metal germano-silicide layer. 
   
   
       16 . The semiconductor structure of  claim 11  further comprising:
 a first contact etch stop layer having a tensile stress over the NMOS device; and   a second contact etch stop layer having a compressive stress over the PMOS device.   
   
   
       17 . A method for forming a semiconductor structure, the method comprising:
 providing a semiconductor substrate;   forming an NMOS device at a surface of the semiconductor substrate, the NMOS device comprising a Schottky source/drain extension region; and   forming a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials.   
   
   
       18 . The method of  claim 17 , wherein the Schottky source/drain extension region is performed simultaneously with the formation of a source/drain silicide region of the PMOS device. 
   
   
       19 . The method of  claim 18 , wherein the step of forming the NMOS device comprises:
 forming a gate stack on the semiconductor substrate;   forming a thick spacer on a sidewall of the gate stack;   implanting an n-type impurity to form a source/drain region;   thinning the thick spacer to form a thin spacer; and   reacting a top portion of the semiconductor substrate adjacent the thin spacer to form the Schottky source/drain extension region substantially aligned to an outer edge of the thin spacer.   
   
   
       20 . The method of  claim 18 , wherein the step of forming the PMOS device comprises:
 forming a gate stack on the semiconductor substrate;   implanting a p-type impurity to form a source/drain extension region;   forming a spacer on a sidewall of the gate stack;   implanting a p-type impurity to form a source/drain region; and   reacting a top portion of the source/drain region to form the source/drain silicide region of the PMOS device, wherein the step of reacting is performed simultaneously with a step of forming the Schottky source/drain extension region.   
   
   
       21 . The method of  claim 18 , wherein the Schottky source/drain extension region has a work function of less than about 4.25 eV. 
   
   
       22 . The method of  claim 17  further comprising forming a contact etch stop layer over the NMOS device and the PMOS device, wherein the contact etch stop layer has a tensile stress. 
   
   
       23 . The method of  claim 17 , wherein the step of forming the NMOS device is free from a step of a source/drain extension implantation. 
   
   
       24 . A method for forming a semiconductor structure, the method comprising:
 providing a semiconductor substrate;   forming an NMOS device at a surface of the semiconductor substrate comprising:
 forming a first gate stack on the semiconductor substrate; 
 forming a thick spacer on a sidewall of the first gate stack; 
 implanting an n-type impurity to form a first source/drain region; 
 thinning the thick spacer to form a thin spacer; and 
 reacting a top portion of the semiconductor substrate adjacent the thin spacer to form a Schottky source/drain extension region; and 
   forming a PMOS device at the surface of the semiconductor substrate comprising:
 forming a second gate stack on the semiconductor substrate; 
 implanting a p-type impurity to form a source/drain extension region; 
 forming a spacer on a sidewall of the second gate stack; 
 implanting a p-type impurity to form a second source/drain region; and 
 reacting a top portion of the second source/drain region to form a source/drain silicide region, wherein the Schottky source/drain extension region of the NMOS device and the source/drain silicide region of the PMOS device are simultaneously formed. 
   
   
   
       25 . The method of  claim 24 , wherein the Schottky source/drain extension region and the source/drain silicide region comprise a metal having a work function of lower than about 4.25 eV. 
   
   
       26 . The method of  claim 24 , wherein the Schottky source/drain extension region and the source/drain silicide region comprise-a metal having a work function close to a conduction band of silicon. 
   
   
       27 . The method of  claim 24  further comprising forming a contact etch stop layer over the NMOS device and the PMOS device, wherein the contact etch stop layer has a tensile stress. 
   
   
       28 . The method of  claim 24 , wherein the step of forming the NMOS device is free from a step of a source/drain extension implantation. 
   
   
       29 . A method for forming a semiconductor structure, the method comprising:
 providing a base semiconductor substrate comprising a PMOS region and an NMOS region, wherein the base semiconductor substrate has a first valence band;   forming an additional semiconductor layer only on the base semiconductor substrate in the PMOS region, wherein the additional semiconductor layer has a second valence band lower than the first valence band;   forming an NMOS device in the NMOS region comprising:
 forming a first gate stack on the base semiconductor substrate; and 
 forming a first Schottky source/drain extension region adjacent the first gate stack; and 
   forming a PMOS device in the PMOS region comprising:
 forming a second gate stack over the additional semiconductor layer; and 
 forming a second Schottky source/drain extension region adjacent the second gate stack, wherein the second Schottky source/drain extension region has a bottom surface lower than a top surface of the additional semiconductor layer, and wherein the step of forming the first and the second Schottky source/drain extension regions are simultaneously performed. 
   
   
   
       30 . The method of  claim 29 , wherein the bottom surface of the second Schottky source/drain extension region is between the top surface and a bottom surface of the additional semiconductor layer. 
   
   
       31 . The method of  claim 29 , wherein the bottom surface of the second Schottky source/drain extension region is level with or lower than a bottom surface of the additional semiconductor layer. 
   
   
       32 . The method of  claim 29 , wherein the base semiconductor substrate is a silicon substrate, the additional semiconductor layer is a silicon-germanium layer, and wherein the method further comprises forming a silicon layer on the silicon-germanium layer before the step of forming the PMOS device. 
   
   
       33 . The method of  claim 29  further comprising:
 forming a first contact etch stop layer having a tensile stress over the NMOS device; and   forming a second contact etch stop layer having a compressive stress over the PMOS device.