Coupling well structure for improving HVMOS performance

Abstract

A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

1 . A semiconductor structure comprising:
 a substrate;   a first well region of a first conductivity type overlying the substrate;   a second well region of a second conductivity type opposite the first conductivity type overlying the substrate;   a cushion region between and adjoining the first and the second well regions;   an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;   a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region; and   a gate electrode on the gate dielectric.   
   
   
       2 . The semiconductor structure of  claim 1 , wherein the cushion region is an overlap region of the first and the second well regions. 
   
   
       3 . The semiconductor structure of  claim 1 , wherein the cushion region is a space between the first and the second well regions. 
   
   
       4 . The semiconductor structure of  claim 1  further comprising a third well region of the first conductivity type overlying the substrate, wherein the third well region is on an opposite side of the second well region than the first well region, and wherein the gate dielectric extends over the third well region. 
   
   
       5 . The semiconductor structure of  claim 4  further comprising a second cushion region between the second and the third well regions. 
   
   
       6 . The semiconductor structure of  claim 5 , wherein one of the first and the second cushion regions is an overlap region, and the other is a spacing between neighboring well regions. 
   
   
       7 . The semiconductor structure of  claim 1 , wherein the cushion region has a width of between about 10 Å and about 3 μm. 
   
   
       8 . The semiconductor structure of  claim 7 , wherein the width is between about 0.3 μm and about 0.5 μm. 
   
   
       9 . The semiconductor structure of  claim 1 , wherein the first conductivity type is selected from the group consisting of p-type and n-type. 
   
   
       10 . The semiconductor structure of  claim 1  further comprising:
 a drain region in the first well region and adjoining the insulation region; and   a source region in the second well region and adjacent an edge of the gate electrode, wherein the source region and the drain region are of the first conductivity type.   
   
   
       11 . A semiconductor structure comprising:
 a substrate;   a first well region of a first conductivity type overlying the substrate;   a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have an overlap region;   an insulation region extending from a top surface of the first well region into the first well region;   a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region; and   a gate electrode on the gate dielectric.   
   
   
       12 . The semiconductor structure of  claim 11 , wherein the overlap region has a width of between about 10 Å and about 3 μm. 
   
   
       13 . The semiconductor structure of  claim 12 , wherein the width is between about 0.3 μm and about 0.5 μm. 
   
   
       14 . A semiconductor structure comprising:
 a substrate;   a first well region having a first impurity of a first conductivity type overlying the substrate;   a second well region having a second impurity of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have a space therebetween;   an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;   a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region; and   a gate electrode on the gate dielectric.   
   
   
       15 . The semiconductor structure of  claim 14 , wherein the space has a width of between about 10 Å and about 3 μm. 
   
   
       16 . The semiconductor structure of  claim 15 , wherein the width is between about 0.3 μm and about 0.5 μm.