Fully Depleted SOI Multiple Threshold Voltage Application

Abstract

An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

1 . An integrated circuit comprising:
 a substrate;   a buried dielectric formed in said substrate, the buried dielectric having a first thickness in a first region and a second thickness in a second region, the buried dielectric having a substantially planar top surface; and   a semiconductor layer overlying said buried dielectric.   
   
   
       2 . The integrated circuit of  claim 1 , wherein a substantial portion of the substrate comprises crystalline silicon. 
   
   
       3 . The integrated circuit of  claim 1 , wherein said semiconductor layer overlying the buried dielectric comprises strained silicon. 
   
   
       4 . The integrated circuit of  claim 1 , wherein said semiconductor layer overlying the buried dielectric comprises a germanium containing semiconductor material. 
   
   
       5 . The integrated circuit of  claim 1 , further comprising a step between said first and second regions, wherein said step is about 200 angstroms or less. 
   
   
       6 . The integrated circuit of  claim 1 , further comprising a fully depleted silicon-on-insulator transistor formed in said semiconductor layer. 
   
   
       7 . The integrated circuit of  claim 1 , wherein the buried dielectric comprises silicon oxide. 
   
   
       8 . The integrated circuit of  claim 1 , wherein the buried dielectric comprises nitrided oxide. 
   
   
       9 . The integrated circuit of  claim 1 , wherein the buried dielectric comprises hydrogenated oxide. 
   
   
       10 . The integrated circuit of  claim 1 , wherein the buried dielectric comprises Al x O y , wherein x is about 2 and y is about 3. 
   
   
       11 . The integrated circuit of  claim 1 , wherein the buried dielectric comprises silicon carbide. 
   
   
       12 . The integrated circuit of  claim 1 , wherein the first region is designated for a first application requiring a first threshold voltage and wherein the second region is designated for a second application requiring a second threshold voltage. 
   
   
       13 . The integrated circuit of  claim 12 , wherein the first application is a core application having the first threshold voltage and the second application is an input/output application having the second threshold voltage, wherein the difference between the first threshold voltage and the second threshold voltage is about 0.45 eV or less. 
   
   
       14 . The integrated circuit of  claim 13 , wherein the first threshold voltage is less than about 1.8 eV. 
   
   
       15 . The integrated circuit of  claim 5 , wherein said step is a gradient region and further comprising a forbidden region overlying said gradient region wherein no active devices are formed. 
   
   
       16 . A semiconductor chip having a first region and a second region, the semiconductor chip comprising:
 a substrate;   a semiconductor layer overlying the substrate;   a buried dielectric under the semiconductor layer, the buried dielectric having a first thickness in said first region and a second thickness in said second region, the buried dielectric having a substantially planar top surface;   a first transistor having a first gate electrode and a second transistor having a second gate electrode formed in said first region; and   a third transistor having a third gate electrode and a fourth transistor having a fourth gate electrode formed in said second region.   
   
   
       17 . The semiconductor chip of  claim 16 , wherein:
 said first gate electrode is formed of a first material and has a first concentration of a first impurity therein and said second gate electrode is formed of a second material and has a second concentration of a second impurity therein; and   said third gate electrode is formed of a third material and has a third concentration of a third impurity therein and said fourth gate electrode is formed of a fourth material and has a fourth concentration of a fourth impurity therein.   
   
   
       18 . The semiconductor chip of  claim 17 , wherein said first material and said third material are substantially the same. 
   
   
       19 . The semiconductor chip of  claim 17 , wherein said second material and said fourth material are substantially the same. 
   
   
       20 . The semiconductor chip of  claim 17 , wherein said first and second concentrations have a ratio equal to about 105 or less. 
   
   
       21 . The semiconductor chip of  claim 17 , wherein said third and fourth concentrations have a ratio equal to about 105 or less. 
   
   
       22 . The semiconductor chip of  claim 17 , wherein said first and third impurities are the same impurity. 
   
   
       23 . The semiconductor chip of  claim 17 , wherein said second and fourth impurities are the same impurity. 
   
   
       24 . The semiconductor chip of  claim 17 , wherein said first and third gate electrodes comprise a silicide of silicon and a first metal and wherein said second and fourth gate electrodes comprise a silicide of silicon and a second metal. 
   
   
       25 . The semiconductor chip of  claim 24 , wherein said second and fourth gate electrodes further comprise said first metal. 
   
   
       26 . The semiconductor chip of  claim 16 , further comprising:
 a gate dielectric having a first gate dielectric thickness underlying said first and second gate electrodes; and   a gate dielectric having a second gate dielectric thickness underlying said third and fourth gate electrodes, wherein said second thickness varies from said first thickness by a predetermined amount.   
   
   
       27 . The semiconductor chip of  claim 16 , wherein the first transistor has a first gate dielectric thickness that is thinner than the second transistor's gate dielectric thickness. 
   
   
       28 . The semiconductor chip of  claim 16 , wherein the first and third gate electrodes comprise titanium. 
   
   
       29 . The semiconductor chip of  claim 17 , wherein the third and fourth gate electrodes comprise platinum. 
   
   
       30 . The semiconductor chip of  claim 27 , wherein the first gate dielectric thickness ranges between about 8 angstroms and about 20 angstroms. 
   
   
       31 . The semiconductor chip of  claim 27 , wherein the second transistor's gate dielectric thickness ranges between about 20 angstroms and about 100 angstroms. 
   
   
       32 . The semiconductor chip of  claim 16 , further comprising a step in said buried dielectric and wherein said step is a gradient region and further comprising a forbidden region overlying said gradient region wherein no active devices are formed. 
   
   
       33 . The semiconductor chip of  claim 16 , wherein the first transistor is a fully depleted silicon-on-insulator p-channel metal oxide semiconductor transistor (FD SOI PMOS) with a first work function ranging between about 4.7 electron-volts and about 5.0 electron-volts, the second transistor is an FD SOI n-channel metal oxide semiconductor (NMOS) device with a second work function ranging between about 4.2 electron-volts and about 4.5 electron-volts, the third transistor is an FD SOI PMOS device with a third work function ranging between about 4.4 electron-volts and about 4.7 electron-volts, and the fourth transistor is an FD SOI NMOS device with a fourth work function ranging between about 4.5 electron-volts and about 4.8 electron-volts