US2008277144A1PendingUtilityA1

Method for indicating quality of a circuit board

Assignee: SILICONWARE PRECISION INDUSTRIES CO LTDPriority: May 6, 2004Filed: Jul 21, 2008Published: Nov 13, 2008
Est. expiryMay 6, 2024(expired)· nominal 20-yr term from priority
H05K 3/242H05K 3/403H05K 2201/09781H05K 1/0269H05K 2203/175H05K 2201/0919H05K 3/0052H05K 3/4602H05K 2203/163Y10T29/49128
54
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Claims

Abstract

A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

Claims

exact text as granted — not AI-modified
1 - 13 . (canceled) 
     
     
         14 . A method for indicating quality of a circuit board with a quality-indicator mark, comprising the steps of:
 providing a circuit board having a plurality of circuit board units, wherein each of the circuit board units has an inner-layer circuit structure, and a plating bus is formed around each of the circuit board units and extended to form a plating trace in the inner-layer circuit structure;   inspecting whether the inner-layer circuit structure of each of the circuit board units is good; if yes, maintaining the connection between the plating trace and the plating bus of the circuit board unit; if no, breaking the connection between the plating trace and the plating bus of the circuit board unit; and   forming at least one circuit structure on the inner-layer circuit structure of each of the circuit board units, and forming a conductive structure on the plating trace to provide a conductive mark on a surface of the circuit board unit, as well as forming a metal protective layer via the plating bus on the at least one circuit structure of the circuit board unit, such that the conductive mark formed with the metal protective layer indicates that the corresponding circuit board unit has the plating bus being connected to the plating trace and the inner-layer circuit structure thereof is good.   
     
     
         15 . The method of  claim 14 , wherein a solder mask layer is formed on surfaces of the circuit board and has a plurality of openings for exposing the conductive marks and input/output connections of the circuit board units. 
     
     
         16 . The method of  claim 15 , wherein the input/output connections include bonding pads and ball pads. 
     
     
         17 . The method of  claim 14 , wherein the metal protective layer is a nickel/gold metal layer. 
     
     
         18 . The method of  claim 14 , wherein the circuit board units are divided by a plurality of transverse and longitudinal cutting lines, and the plating bus is formed at the transverse and longitudinal cutting lines. 
     
     
         19 . The method of  claim 14 , wherein the plating trace is provided with a conductive via at a terminal thereof, and the conductive mark is formed on the conductive via and located at the at least one circuit structure of the circuit board unit. 
     
     
         20 . The method of  claim 14 , wherein the conductive mark is selectively formed on a front surface or a back surface of the circuit board unit. 
     
     
         21 . The method of  claim 14 , wherein the conductive mark is selectively located outside an area encompassed by the plating bus on the circuit board unit or within the area encompassed by the plating bus free of a circuit layout of the circuit board unit.

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