Phase change memory device and method for manufacturing the same

Abstract

A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.

1 . A phase change memory device having a phase change layer, the phase change memory device comprising:
 a switching element;   a heater formed over the switching element;   a heat sink formed between the switching element and the heater, wherein the heat sink quickly cools heat transferred to the phase change layer from the heater.   
   
   
       2 . The phase change memory device according to  claim 1 , wherein the switching element comprises a PN diode. 
   
   
       3 . The phase change memory device according to  claim 1 , wherein the heater comprises any one of a TiW layer, a TiAIN layer, and a TiN layer. 
   
   
       4 . The phase change memory device according to  claim 1 , wherein the heat sink is formed of tungsten or tungsten silicide. 
   
   
       5 . A phase change memory device including a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region, the phase change memory device comprising:
 a first insulation layer formed on the silicon substrate, the first insulation layer having a plurality of first contact holes and second contact holes formed on sides of the plurality of first contact holes;   PN diodes formed in the first contact holes;   heat sinks formed in the first contact holes on the PN diode to fill the first contact holes;   contact plugs formed to fill the second contact holes;   a second insulation layer formed on the first insulation layer including the heat sinks and the contact plugs, the second insulation layer having third contact holes exposing the heat sinks;   heaters formed in the third contact holes; and   stack patterns formed to contact the heaters, each stack pattern comprising a phase change layer and a top electrode.   
   
   
       6 . The phase change memory device according to  claim 5 , wherein the first contact holes have a width in the range of 100˜1,000 Å. 
   
   
       7 . The phase change memory device according to  claim 5 , wherein the first contact holes are separated from one another by a distance in the range of 10˜2,000 Å. 
   
   
       8 . The phase change memory device according to  claim 5 , wherein the first contact holes are grouped, and the number of first contact holes in the group corresponds to a multiple of 2. 
   
   
       9 . The phase change memory device according to  claim 5 , wherein the second contact holes have a width greater than a width of the first contact holes. 
   
   
       10 . The phase change memory device according to  claim 5 , wherein each PN diode comprises a stack pattern comprising an N-type silicon layer and a P-type silicon layer sequentially formed on the N-type impurity region. 
   
   
       11 . The phase change memory device according to  claim 10 , wherein the N-type silicon layer has a concentration lower than a concentration of the N-type impurity region. 
   
   
       12 . The phase change memory device according to  claim 10 , wherein the P-type silicon layer has a concentration higher than a concentration of N-type silicon layer. 
   
   
       13 . The phase change memory device according to  claim 12 , wherein the N-type silicon layer has a concentration in the range of 1×10 18 1×10 20  ions/cm 3 , and the P-type silicon layer has a concentration in the range of 1×10 19 ˜1×10 22  ions/cm 3 . 
   
   
       14 . The phase change memory device according to  claim 5 , wherein the top of the PN diode is below an upper end of the first contact hole by a depth in the range of 100˜3,000 Å. 
   
   
       15 . The phase change memory device according to  claim 5 , further comprising:
 first metal silicide layers interposed between the PN diodes and the heat sinks in the first contact holes and second metal silicide layers interposed between the N-type impurity region and the contact plugs in the second contact holes.   
   
   
       16 . The phase change memory device according to  claim 15 , wherein the metal silicide layers comprise Co silicide or Ti silicide. 
   
   
       17 . The phase change memory device according to  claim 15 , further comprising:
 barrier layers interposed between the first metal silicide layers and the heat sinks in the first contact holes, and between the second metal silicide layers and the contact plugs in the second contact holes.   
   
   
       18 . The phase change memory device according to  claim 5 , wherein the heat sinks comprise tungsten or tungsten silicide. 
   
   
       19 . The phase change memory device according to  claim 5 , wherein the third contact holes have a width in the range of 100˜1,000 Å. 
   
   
       20 . The phase change memory device according to  claim 5 , wherein the heaters comprise any one of a TiW layer, a TiAIN layer, and a TiN layer. 
   
   
       21 . The phase change memory device according to  claim 5 , wherein the stack pattern of the phase change layer and the top electrode is stacked in a direction perpendicular to the active region. 
   
   
       22 . The phase change memory device according to  claim 5 , wherein the phase change layer comprises at least one of Ge, Sb, and Te. 
   
   
       23 . The phase change memory device according to  claim 21 , wherein the phase change layer is doped with at least one of oxygen, nitrogen, and silicon. 
   
   
       24 . A method for manufacturing a phase change memory device having silicon substrate with a bar-type active region and an N-type impurity region formed in a surface of the active region, comprising the steps of:
 forming a first insulation layer on the silicon substrate;   etching the first insulation layer to define a plurality of grouped first contact holes;   forming PN diodes in the first contact holes;   etching the first insulation layer to define second contact holes at sides of the grouped first contact holes;   forming heat sinks in the first contact holes on the PN diodes and forming contact plugs in the second contact holes;   forming a second insulation layer having third contact holes exposing the heat sinks on the first insulation layer;   forming heaters in the third contact holes; and   forming stack patterns to contact the heaters, each stack pattern comprising a phase change layer and a top electrode.   
   
   
       25 . The method according to  claim 24 , wherein the first contact holes are defined to have a width in the range of 100˜1,000 Å. 
   
   
       26 . The method according to  claim 24 , wherein the first contact holes are defined to be separated from one another by a distance in the range of 10˜2,000 Å. 
   
   
       27 . The method according to  claim 24 , wherein the number of the grouped first contact holes corresponds to a multiple of 2. 
   
   
       28 . The method according to  claim 24 , wherein the second contact holes are defined to have a width greater than a width of the first contact holes. 
   
   
       29 . The method according to  claim 24 , wherein the PN diodes are formed such that the PN diodes are recessed to a depth in the range of 100˜3,000 when measured from upper ends of the first contact holes. 
   
   
       30 . The method according to  claim 24 , wherein the PN diodes are formed as a stack pattern comprising an N-type silicon layer and a P-type silicon layer. 
   
   
       31 . The method according to  claim 30 , wherein the step of forming the stack pattern comprising the N-type silicon layer and the P-type silicon layer comprises the steps of:
 forming the N-type silicon layer on the N-type impurity region exposed by the first contact holes using a selective epitaxial growth process, such that the N-type silicon layer is recessed in the first contact holes; and   ion-implanting P-type impurities in an upper portion of the N-type silicon layer to form the P-type silicon layer.   
   
   
       32 . The method according to  claim 31 , wherein the N-type silicon layer is formed to have a concentration lower than a concentration of the N-type impurity region. 
   
   
       33 . The method according to  claim 32 , wherein the N-type silicon layer is formed to have a concentration in the range of 1×10 18 ˜1×10 20  ions/cm 3 . 
   
   
       34 . The method according to  claim 31 , wherein the P-type silicon layer is formed to have a concentration higher than a concentration of the N-type silicon layer. 
   
   
       35 . The method according to  claim 34 , wherein the P-type silicon layer is formed to have a concentration in the range of 1×10 19 ˜1×10 22  ions/cm 3 . 
   
   
       36 . The method according to  claim 24 , further comprising:
 after the step of defining the second contact holes and before the step of forming the heat sinks and the contact plugs,   forming first metal silicide layers on the PN diodes in the first contact holes and forming second metal silicide layers on the N-type impurity region in the second contact holes.   
   
   
       37 . The method according to  claim 36 , wherein the first and second metal silicide layers comprise Co silicide or Ti silicide. 
   
   
       38 . The method according to  claim 36 , further comprising:
 after the step of forming the first and second metal silicide layers and before the step of forming the heat sinks and the contact plugs,   forming a barrier layer; and   annealing the barrier layer.   
   
   
       39 . The method according to  claim 24 , wherein the heat is sinks and the contact plugs are formed to comprise tungsten or tungsten silicide. 
   
   
       40 . The method according to  claim 24 , wherein the third contact holes are defined to have a width in the range of 100˜1,000 Å. 
   
   
       41 . The method according to  claim 24 , wherein the heaters are formed to comprise any one of a TiW layer, a TiAIN layer and a TiN layer. 
   
   
       42 . The method according to  claim 24 , wherein the stack pattern of the phase change layer and the top electrode is formed in a direction perpendicular to the active region. 
   
   
       43 . The method according to  claim 24 , wherein the phase change layer is formed of a material comprising at least one of Ge, Sb, and Te. 
   
   
       44 . The method according to  claim 43 , wherein the phase change layer is doped with at least one of oxygen, nitrogen, and silicon.