Semiconductor transistor having a stressed channel

Abstract

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases I DSAT and I DLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

1 . A transistor comprising:
 a first semiconductor material having a first lattice constant;   a gate dielectric layer over said first semiconductor material;   a gate electrode on said gate dielectric layer; and   epitaxial source and drain regions on opposite sides of said gate electrode;   wherein said epitaxial source and drain regions are a semiconductor material having a lattice constant which is different from said first semiconductor material lattice constant, said epitaxial source and drain regions causing stress across said first semiconductor material between said epitaxial source and drain regions.   
   
   
       2 . The transistor of  claim 1 , wherein said epitaxial source and drain regions are formed in source and drain recesses in said first semiconductor material. 
   
   
       3 . The transistor of  claim 1 , wherein said stress is a compressive stress. 
   
   
       4 . The transistor of  claim 3 , wherein said first semiconductor material is silicon and wherein said second semiconductor material is a silicon germanium alloy. 
   
   
       5 . The transistor of  claim 4 , wherein said silicon germanium alloy comprises between 15-20 atomic percent germanium. 
   
   
       6 . The transistor of  claim 3 , wherein said second semiconductor material further comprises a p-type dopant. 
   
   
       7 . The transistor of  claim 6 , wherein said p-type dopant is boron. 
   
   
       8 . The transistor of  claim 1 , wherein said stress is a tensile stress. 
   
   
       9 . The transistor of  claim 8 , wherein said first semiconductor material is silicon and wherein said second semiconductor material is a silicon carbon alloy. 
   
   
       10 . The transistor of  claim 8 , wherein said second semiconductor material further comprises an n-type dopant. 
   
   
       11 . The transistor of  claim 10 , wherein said n-type dopant is selected from the group consisting of phosphorous and arsenic.