Wafer level sensing package and manufacturing process thereof

Abstract

A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.

1 . A sensing wafer structure with a stress release layer, comprising:
 a wafer, having a wafer surface and a wafer backside opposite to the wafer surface, wherein the wafer comprises a plurality of sensing chips each having a sensing portion and a plurality of pads; and   a stress release layer, covered on the wafer surface, and exposing the pads and the sensing portions, so as to form a plurality of pad areas and sensing areas.   
   
   
       2 . The sensing wafer structure with a stress release layer according to  claim 1 , wherein the wafer backside of the wafer has a plurality of cavities at a position corresponding to each sensing area. 
   
   
       3 . The sensing wafer structure with a stress release layer according to  claim 2 , wherein the wafer backside further has a reinforcement plate. 
   
   
       4 . The sensing wafer structure with a stress release layer according to  claim 3 , wherein the reinforcement plate has a through hole corresponding to the position of the cavity. 
   
   
       5 . A wafer level sensing package, constituted by a plurality of sensing chips and a plurality of reserved scribe lines, the package comprising:
 a wafer, constituted by a plurality of sensing chips and a plurality of scribe lines, and having a wafer surface and a wafer backside opposite to the wafer surface, wherein each sensing chip on the wafer surface has an active surface, and the active surface further has a sensing area and a plurality of pads;   an stress release layer, located on the active surface of each sensing chip of the wafer, and exposing the sensing area and the pads;   a conductive metal layer, disposed on the surface of the stress release layer and electrically coupled to the pads, wherein a plurality of re-distributed pads is formed on the conductive metal layer; and   a plurality of conductive bumps, electrically coupled to each of the re-distributed pads respectively.   
   
   
       6 . The wafer level sensing package according to  claim 5 , wherein a cavity is disposed on a wafer backside opposite to the sensing area of each sensing chip of the wafer, and is at the position corresponding to the sensing area. 
   
   
       7 . The wafer level sensing package according to  claim 6 , wherein the wafer backside further has a reinforcement plate. 
   
   
       8 . The wafer level sensing package according to  claim 6 , wherein the reinforcement plate has a through hole corresponding to the position of the cavity. 
   
   
       9 . A manufacturing process of a wafer level sensing package, comprising:
 providing a wafer having a plurality of sensing chips, wherein the wafer has a wafer surface, and each sensing chip on the wafer surface further has a sensing area and a plurality of pads;   forming a stress release layer on the wafer surface to expose the sensing area and the pads;   cladding a photoresist layer on the stress release layer to shelter the sensing area and the pads;   patterning the photoresist layer to expose the pads and a plurality of re-distributed pad reservation areas connected to the pads;   forming a conductive metal layer to form a re-distributed metal layer on the photoresist layer and the pad areas, and form a re-distributed pad area in the re-distributed pad reservation areas;   removing the photoresist layer to expose the stress release layer and the conductive metal layer;   forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer to shelter the sensing area and the pads;   patterning the re-cladding photoresist layer to form a plurality of holes in the re-cladding photoresist layer above the re-distributed pad area; and   forming a conductive bump in each hole to electrically connect to the conductive metal layer.   
   
   
       10 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein the step of forming a conductive bump in each hole to electrically connect to the conductive metal layer further comprises a step of removing the re-cladding photoresist layer and a step of performing a reflow process, and the orders of the two steps are exchangeable. 
   
   
       11 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein the conductive metal layer is formed by electro-plating, vapor deposition, or sputtering. 
   
   
       12 . The manufacturing process of a wafer level sensing package according to  claim 9 , after the step of forming a conductive bump in each hole to electrically connect to the conductive metal layer, further comprising a step of cutting along adjacent positions of each sensing chip of the wafer to form a plurality of granular sensing chip packages. 
   
   
       13 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein a composition of the stress release layer is one selected from a group consisting of PI, BCB, and silica gel. 
   
   
       14 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein the conductive bump is formed by electro-plating. 
   
   
       15 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein a conductive bump is formed by directly disposing a solder ball in each hole, and the hole is pre-coated with a solder flux or solder paste. 
   
   
       16 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein the conductive bump is a gold bump or a solder bump. 
   
   
       17 . The manufacturing process of a wafer level sensing package according to  claim 9 , wherein the photoresist layer or re-cladding photoresist layer is cladded by a general thick film forming process comprising stencil printing, spin-coating, or preformed plastic hot pressing.