Wafer level chip scale package having an enhanced heat exchange efficiency with an emf shield and a method for fabricating the same

Abstract

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

1 . A wafer level chip scale package, comprising:
 a semiconductor chip having a plurality of bonding pads on an upper face thereof;   an insulation layer, disposed over the upper face of the semiconductor chip, having openings that expose portions of the bonding pad; and   a metal plate covering an upper face of the insulation layer and side faces of the semiconductor chip which is electrically insulated from the bonding pads.   
     
     
         2 . The wafer level chip scale package according to  claim 1 , wherein the metal plate is formed over a partial portion of the side faces of the semiconductor chip. 
     
     
         3 . The wafer level chip scale package according to  claim 1 , further comprising a metal seed layer interposed below the metal plate and the insulation layer. 
     
     
         4 . A method for fabricating a wafer level chip scale package, comprising the steps of:
 forming a blind groove in a scribe lane of a wafer by carrying out a first sawing process on the wafer along the scribe lane, wherein the wafer is divided by the scribe lane and has semiconductor chips formed with bonding pads exposed by openings formed in an insulation layer formed over an upper face of the semiconductor chip;   forming a metal plate over the insulation layer, wherein the metal plate fills the blind groove and is insulated with the bonding pads; and   separating the semiconductor chips from the wafer by carrying out a second sawing process along the scribe lane.   
     
     
         5 . The method according to  claim 4 , wherein the first sawing process is carried out using a first blade which has substantially the same width as the scribe lane, and the second sawing process is carried out using a second blade having narrower width than the scribe lane. 
     
     
         6 . A wafer level chip scale package, comprising:
 a semiconductor chip having a plurality of ground bonding pads and signal bonding pads over an upper face of the semiconductor chip;   a first insulation layer, disposed over the upper face of the semiconductor chip, having openings which expose portions of the ground bonding pads and the signal bonding pads;   a first metal plate insulated with the signal bonding pads and covering the first insulation layer and side faces of the semiconductor chip; and   a second metal plate disposed under a lower face of the semiconductor chip.   
     
     
         7 . The wafer level chip scale package according to  claim 6 , wherein the first metal plate is formed at the side face of the semiconductor chip and has substantially the same height as the height of the side face. 
     
     
         8 . The wafer level chip scale package according to  claim 6 , wherein the first and second metal plates are made of one of copper (Cu) or copper alloy. 
     
     
         9 . The wafer level chip scale package according to  claim 6 , further comprising a second insulation layer formed between the lower face of the semiconductor chip and the second metal plate. 
     
     
         10 . The wafer level chip scale package according to  claim 6 , wherein a portion of the first metal plate is formed in an island shape over an upper face of the signal bonding pad. 
     
     
         11 . A method for fabricating a wafer level chip scale package, comprising the steps of:
 forming a blind groove having a certain depth in a scribe lane of a wafer by carrying out a first sawing process on the wafer along the scribe lane, wherein the wafer is divided by the scribe lane and has semiconductor chips formed with a plurality of ground bonding pads and signal bonding pads exposed by openings formed in a first insulation layer formed over an upper face of the semiconductor chip;   forming a first metal plate over the insulation layer, wherein the first metal plate is insulated away from the signal bonding pads and the first metal plate is electrically connected to the ground bonding pads;   polishing a lower face of the wafer to expose the first metal plate filled in the blind groove;   forming a second metal plate connected with the first metal plate exposed to the lower face of the wafer; and   separating a plurality of chip level packages from the wafer by carrying out a second sawing process on the wafer along the scribe lane.   
     
     
         12 . The method according to  claim 11 , wherein the first and second metal plates are formed by a plating process and the first and second metal plates are made of one of copper (Cu) or copper alloy. 
     
     
         13 . The method according to  claim 11 , wherein the first sawing process is carried out using a first blade which has substantially the same width as the scribe lane, and the second sawing process is carried out using a second blade having a narrower width than the scribe lane. 
     
     
         14 . The method according to  claim 11 , wherein the step of forming the first metal plate includes the steps of:
 forming a first metal seed layer over the bonding pads and over the first insulation layer including the surface of the blind groove;   forming a mask pattern over the first metal seed layer next to the signal bonding pad;   forming the first metal plate over the exposed mask pattern; and   removing the mask pattern and the first metal seed layer therebelow.   
     
     
         15 . A wafer level chip scale package, comprising:
 a semiconductor chip having a circuit unit and bonding pads electrically connected to the circuit unit;   through electrodes passing through an upper face of the semiconductor chip and through a lower face of the semiconductor opposite to the upper face;   redistribution units disposed over the upper face of the semiconductor chip and the redistribution units provided with a first end portion formed integrally with the through electrode and a second end portion opposite to the first end portion and electrically connected with the bonding pads; and   a dummy conductive pattern disposed over the upper face of the semiconductor chip and electrically insulated away from the redistribution units.   
     
     
         16 . The wafer level chip scale package according to  claim 15 , further comprising a dummy metal seed pattern interposed between the dummy conductive pattern and the upper face of the semiconductor chip. 
     
     
         17 . The wafer level chip scale package according to  claim 15 , wherein the redistribution and the dummy conductive pattern have substantially the same thickness. 
     
     
         18 . A method for fabricating a wafer level chip scale package, comprising the steps of:
 forming through holes passing through an upper face of a semiconductor chip and through a lower face opposite to the upper face, wherein the upper surface of the semiconductor chip is formed with bonding pads electrically connected to a circuit unit;   forming a metal seed layer over an inner surface of the semiconductor chip formed by the through holes and the upper face of the semiconductor chip;   forming mask patterns having a band shape over the metal seed layer along a periphery of the redistribution regions respectively connecting the through hole and the bonding pad corresponding to the through hole;   forming through electrodes inside the through holes exposed by using the mask patterns, forming redistribution units within each redistribution region and forming a dummy conductive pattern outside of each mask pattern;   removing the mask patterns from the metal seed layer; and   removing the metal seed layer formed at a position corresponding to the mask pattern from the upper face of the semiconductor chip.   
     
     
         19 . The method according to  claim 18 , wherein the step of forming the mask patterns over the metal seed layer includes the steps of:
 forming a photoresist film over the metal seed layer; and   patterning the photoresist film by exposing and developing the photoresist film.   
     
     
         20 . The method according to  claim 18 , wherein the step of forming the mask patterns over the metal seed layer includes the steps of:
 providing flowable mask material over the metal seed layer in shape of a band; and   curing the flowable mask material.