Trench-Gate Field Effect Transistors and Methods of Forming the Same

Abstract

A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

1 - 17 . (canceled) 
   
   
       18 . A dual-gate trench field effect transistor comprising:
 an active region and a termination region, the active region including gate trenches extending into a semiconductor region, and the termination region including a termination trench extending into the semiconductor region, the gate trenches including an outer-most gate trench laterally spaced from the termination trench;   a shield dielectric layer lining lower sidewalls of each gate trench as well as lower and upper sidewalls of the termination trench;   a shield electrode disposed in each gate trench and in the termination trench, the shield electrode in each gate trench extending in a lower portion of the gate trench, and the shield electrode in the termination trench extending through upper and a lower portions of the termination trench;   a gate dielectric layer lining upper sidewalls of each gate trench;   a gate electrode disposed in each gate trench but not in the termination trench, each gate electrode being insulted from an underlying shield electrode by a laterally-extending dielectric layer; and   a body region extending between and abutting sidewalls of: (i) every two adjacent gate trenches, and (ii) the outer-most gate trench and the termination trench, each of the body regions extending between two adjacent gate trenches including source regions adjacent corresponding gate trench sidewalls, and the body region extending between the outer-most gate trench and the termination trench including a source region adjacent a sidewall of the outer-most gate trench, wherein the body region and source regions are of opposite conductivity type.   
   
   
       19 . The dual-gate trench field effect transistor of  claim 18  wherein the gate trenches and the termination trench have substantially the same depth and width. 
   
   
       20 . The dual-gate trench field effect transistor of  claim 18  wherein the shield dielectric layer is thicker than the gate dielectric layer. 
   
   
       21 . The field effect transistor of  claim 18  wherein the semiconductor region comprises:
 a substrate region; and   a drift region over the substrate region, the body regions extending over the drift region, the drift region having a lower doping concentration than the substrate region   
   
   
       22 . The dual-gate trench field effect transistor of  claim 21  wherein the gate trenches and the termination trench extend into and terminate within the substrate. 
   
   
       23 . The dual-gate trench field effect transistor of  claim 18  wherein each body region extending every two adjacent gate trench and the body region extending between the outer-most gate trench and the termination trench includes a heavy body region that has a higher doping concentration than the body regions. 
   
   
       24 . The dual-gate trench field effect transistor of  claim 23  further comprising a source interconnect electrically contacting the source regions and the body regions. 
   
   
       25 . The dual-gate trench field effect transistor of  claim 18  wherein no body regions abut an outer sidewall of the termination trench. 
   
   
       26 . The dual-gate trench field effect transistor of  claim 18  wherein each gate electrode is recessed in corresponding gate trench, and the shield electrode in the termination trench is not recessed in the termination trench. 
   
   
       27 . A dual-gate trench field effect transistor comprising:
 an active region and a termination region, the active region including gate trenches extending into a semiconductor region, and the termination region including a termination trench extending into the semiconductor region, the gate trenches including an outer-most gate trench laterally spaced from the termination trench, wherein the gate trenches and the termination trench have substantially the same depth and width;   a shield dielectric layer lining lower sidewalls of each gate trench as well as lower and upper sidewalls of the termination trench;   a shield electrode disposed in each gate trench and in the termination trench, the shield electrode in each gate trench extending in a lower portion of the gate trench, and the shield electrode in the termination trench extending through upper and a lower portions of the termination trench;   a gate dielectric layer lining upper sidewalls of each gate trench, wherein the shield dielectric layer is thicker than the gate dielectric layer;   a gate electrode disposed in each gate trench but not in the termination trench, each gate electrode being insulted from an underlying shield electrode by a laterally-extending dielectric layer; and   a body region extending between and abutting sidewalls of: (i) every two adjacent gate trenches, and (ii) the outer-most gate trench and the termination trench, each of the body regions extending between two adjacent gate trenches including source regions adjacent corresponding gate trench sidewalls, and the body region extending between the outer-most gate trench and the termination trench including a source region adjacent a sidewall of the outer-most gate trench, wherein the body region and source regions are of opposite conductivity type.   
   
   
       28 . The field effect transistor of  claim 27  wherein the semiconductor region comprises:
 a substrate region; and   a drift region over the substrate region, the body regions extending over the drift region, the drift region having a lower doping concentration than the substrate region   
   
   
       29 . The dual-gate trench field effect transistor of  claim 28  wherein the gate trenches and the termination trench extend into and terminate within the substrate. 
   
   
       30 . The dual-gate trench field effect transistor of  claim 27  wherein each body region extending between every two adjacent gate trenches and the body region extending between the outer-most gate trench and the termination trench include a heavy body region that has a higher doping concentration than the body regions. 
   
   
       31 . The dual-gate trench field effect transistor of  claim 27  further comprising a source interconnect electrically contacting the source regions and the body regions. 
   
   
       32 . The dual-gate trench field effect transistor of  claim 27  wherein no body regions abut an outer sidewall of the termination trench. 
   
   
       33 . The dual-gate trench field effect transistor of  claim 27  wherein each gate electrode is recessed in corresponding gate trench, and the shield electrode in the termination trench is not recessed in the termination trench.