Power Device Packages Having Thermal Electric Modules Using Peltier Effect and Methods of Fabricating the Same

Abstract

Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

1 . A power device package comprising:
 a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series;   a lead frame attached to the first surface of the thermal electric module by an adhesive member;   one or more power semiconductor chips disposed on and electrically connected to the lead frame;   one or more control semiconductor chips disposed on and electrically connected to the lead frame to control at least one power semiconductor chip; and   a sealing member sealing the thermal electric module, the one or more power semiconductor chips, the one or more control semiconductor chips, and at least a portion of the lead frame so as to expose the second surface of the thermal electric module.   
   
   
       2 . The power device package of  claim 1 , wherein the thermal electric module comprises:
 an impurity element array portion having the n-type impurity elements and the p-type impurity elements arranged in an alternating manner;   a first plurality of conductive members disposed on the impurity element array portion and a second plurality of conductive members disposed below the impurity element array portion, the conductive members electrically connecting the n-type impurity elements and the p-type impurity elements in series;   a power wiring electrically connected to a portion of the conductive members and adapted to convey electrical power to the impurity element array portion from the outside; and   a first insulating member disposed on at least a portion of the first conductive members, and a second insulating member disposed below at least a portion of the second conductive members.   
   
   
       3 . The power device package of  claim 2 , wherein the impurity element array portion comprises a semiconductor substrate,
 wherein the n-type impurity elements comprise n-type impurity regions in the semiconductor substrate, the n-type regions having n-type doped or ion-implanted impurities disposed in the semiconductor substrate, and   wherein the p-type impurity elements comprise p-type impurity regions in the semiconductor substrate, the p-type regions having p-type doped or ion-implanted impurities disposed in the semiconductor substrate.   
   
   
       4 . The power device package of  claim 2 , wherein the conductive members comprise aluminum, an aluminum alloy, copper, a copper alloy, nickel, a nickel alloy, or a combination thereof. 
   
   
       5 . The power device package of  claim 2 , wherein the power wiring is electrically connected to the lead frame and adapted to convey electrical power to the impurity element array portion. 
   
   
       6 . The power device package of  claim 1 , wherein the n-type impurities included in the n-type impurity elements comprise one or more selected from the group consisting of N, P, As, Sb, Bi, S, Se, Te, and Po, and the p-type impurities comprised in the p-type impurity elements comprise one or more selected from the group consisting of B, Al, Ga, In, Tl, Zn, Cd, and Hg. 
   
   
       7 . The power device package of  claim 1 , wherein at least one semiconductor chip is disposed so as to be electrically connected to the lead frame in the form of a flip chip or is electrically connected to the lead frame with at least one wire or at least one solder ball, wherein the at least one semiconductor chip is a power semiconductor chip or a control semiconductor chip. 
   
   
       8 . The power device package of  claim 7 , wherein the at least one wire comprises aluminum or gold. 
   
   
       9 . The power device package of  claim 1 , wherein the one or more power semiconductor chips comprise one or more power metal oxide semiconductor field effect transistors, one or more bipolar junction transistors, one or more insulated-gate bipolar transistors, or one or more diodes, or a combination thereof. 
   
   
       10 . The power device package of  claim 1 , wherein the sealing member comprises an epoxy molding compound, a polyimide, a silicone, a silicone rubber, or a combination thereof. 
   
   
       11 . The power device package of  claim 1 , further comprising a heat sink attached to the second surface of the thermal electric module. 
   
   
       12 . The power device package of  claim 11 , wherein the heat sink comprises aluminum, an aluminum alloy, copper, a copper alloy, an aluminum oxide, a beryllium oxide, an aluminum nitride, a silicon nitride, or an epoxy-based resin, or a combination thereof. 
   
   
       13 . The power device package of  claim 1 , wherein the lead frame adhesive member comprises an elastomer or an epoxy, or a combination thereof. 
   
   
       14 . A power device package comprising:
 a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series;   a wiring pattern disposed on the first surface;   a lead frame attached to the first surface of the thermal electric module by a conductive adhesive member and electrically connected to the wiring pattern;   one or more power semiconductor chips disposed on and electrically connected to the wiring pattern;   one or more control semiconductor chips disposed on and electrically connected to the lead frame or the wiring pattern, or both, to control the at least one power semiconductor chip; and   a sealing member sealing the thermal electric module, the one or more power semiconductor chips, the one or more control semiconductor chips, and at least a portion of the lead frame so as to expose the second surface of the thermal electric module.   
   
   
       15 . The power device package of  claim 14 , wherein the thermal electric module comprises:
 an impurity element array portion having the n-type impurity elements and the p-type impurity elements arranged in an alternating manner;   a first plurality of conductive members disposed on the impurity element array portion and a second plurality of conductive members disposed below the impurity element array portion, the conductive members electrically connecting the n-type impurity elements and the p-type impurity elements in series;   a power wiring electrically connected to a portion of the conductive members and adapted convey electrical power to the impurity element array portion from the outside; and   a first insulating member disposed on at least a portion of the first conductive members, and a second insulating member disposed below at least a portion of the second conductive members.   
   
   
       16 . The power device package of  claim 15 , wherein the impurity element array portion comprises a semiconductor substrate,
 wherein the n-type impurity elements comprise n-type impurity regions in the semiconductor substrate, the n-type regions having n-type doped or ion-implanted impurities disposed in the semiconductor substrate, and   wherein the p-type impurity elements comprise p-type impurity regions in the semiconductor substrate, the p-type regions having p-type doped or ion-implanted impurities disposed in the semiconductor substrate.   
   
   
       17 . The power device package of  claim 15 , wherein the power wiring is electrically connected to the lead frame and adapted to convey electrical power to the impurity element array portion. 
   
   
       18 . The power device package of  claim 14 , wherein the wiring pattern comprises aluminum, an aluminum alloy, copper, or a copper alloy, or a combination thereof. 
   
   
       19 . The power device package of  claim 18 , wherein the wiring pattern further comprises nickel, gold, or an alloy thereof. 
   
   
       20 . The power device package of  claim 14 , wherein the conductive adhesive member comprises a solder, a solder paste, or a silver paste, or a combination thereof. 
   
   
       21 . The power device package of  claim 14 , wherein at least one semiconductor chip is disposed so as to be electrically connected to the lead frame in the form of a flip chip or is electrically connected to the lead frame with at least one wire or at least one solder ball, wherein the at least one semiconductor chip is a power semiconductor chip or a control semiconductor chip. 
   
   
       22 . The power device package of  claim 21 , wherein the at least one wire comprises aluminum or gold. 
   
   
       23 . The power device package of  claim 14 , further comprising a heat sink attached to the second surface of the thermal electric module. 
   
   
       24 . The power device package of  claim 23 , wherein the heat sink comprises aluminum, an aluminum alloy, copper, a copper alloy, an aluminum oxide, a beryllium oxide, an aluminum nitride, a silicon nitride, or an epoxy-based resin, or a combination thereof. 
   
   
       25 . A method of fabricating a power device package, the method comprising:
 assembling a lead frame and a first surface of a thermal electric module together using an adhesive member, the thermal electric module having a second surface opposite to the first surface, a plurality of n-type impurity elements, and a plurality of p-type impurity elements, the n-type impurity elements and the p-type impurity elements being alternately and electrically connected to each other in series;   mounting one or more power semiconductor chips and one or more control semiconductor chips on the lead frame;   electrically connecting at least one power semiconductor chip and at least one control semiconductor chip to the lead frame; and   sealing the thermal electric module, the one or more power semiconductor chips, the one or more control semiconductor chips, and a portion of the lead frame with a sealing member so as to expose the second surface of the thermal electric module.   
   
   
       26 . The method of  claim 25 , wherein assembling the lead frame and the thermal electric module together comprises electrically connecting the thermal electric module and the lead frame. 
   
   
       27 . The method of  claim 25 , after the sealing of the substrate, the power semiconductor chips, and the portion of the lead frame, the method further comprising:
 trimming the leads of the lead frame to leave only some of the leads exposed to the outside of the sealing member; and   bending the exposed leads.   
   
   
       28 . A method of fabricating a power device package, the method comprising:
 forming a wiring pattern on a first surface of a thermal electric module, the thermal electric module having a second surface opposite to the first surface, a plurality of n-type impurity elements, and a plurality of p-type impurity elements, the n-type impurity elements and the p-type impurity elements being alternately and electrically connected to each other in series;   mounting one or more power semiconductor chips on the thermal electric module so as to electrically connect to the wiring pattern;   assembling a lead frame and the first surface of the thermal electric module together using a conductive adhesive member so that the lead frame and the wiring pattern are electrically connected; and   sealing the thermal electric module, the power semiconductor chips, the control semiconductor chips and a portion of the lead frame with a sealing member so as to expose the second surface of the thermal electric module.   
   
   
       29 . The method of  claim 28 , wherein the mounting of the power semiconductor chips on the thermal electric module further comprises mounting one or more control semiconductor chips on the wiring pattern so as to be electrically connected to the wiring pattern. 
   
   
       30 . The method of  claim 28 , wherein assembling the lead frame and the first surface of the thermal electric module together comprises electrically connecting the thermal electric module and the lead frame.