Semiconductor device

Abstract

A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

1 . A semiconductor device comprising:
 a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate;   a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode; and   a second spacer of a high dielectric constant, that is greater than the low dielectric constant, disposed on an upper sidewall of the first gate electrode above the first spacer.   
   
   
       2 . The semiconductor device of  claim 1  further comprising:
 a first impurity junction region disposed on the semiconductor substrate adjacent to a sidewall of the first gate electrode, wherein the first impurity junction region includes an elevated source/drain disposed higher than a surface of the semiconductor substrate.   
   
   
       3 . The semiconductor device of  claim 2 , wherein the first spacer separates the gate conductive layer and the first impurity junction region. 
   
   
       4 . The semiconductor device of  claim 2 , wherein the first spacer includes an oxide layer and the second spacer includes a nitride layer. 
   
   
       5 . The semiconductor device of  claim 2 , wherein the capping pattern includes a nitride layer. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the first spacer has a width equal to or greater than a width of the second spacer and the first and second spacers comprise separately formed unitary layers on the sidewall of the first gate electrode. 
   
   
       7 . The semiconductor device of  claim 1 , further comprising a second gate electrode formed on the semiconductor substrate, wherein an entire sidewall of the second gate electrode is covered with the second spacer of a high dielectric constant. 
   
   
       8 . The semiconductor device of  claim 1 , further comprising:
 a first impurity junction region disposed on the semiconductor substrate adjacent to a sidewall of the first gate electrode; and   a second gate electrode formed on the semiconductor substrate, wherein a second impurity junction region having a top surface even with a surface of the semiconductor substrate is formed in the semiconductor substrate adjacent to the second gate electrode.   
   
   
       9 - 20 . (canceled)