METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS

Abstract

A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

1 . A multilayered gate stack comprising:
 a metal nitrogen-containing layer located on a surface of a high-k gate dielectric, said metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1; and   a Si-containing conductor located directly on a surface of said metal nitrogen-containing layer.   
   
   
       2 . The multilayered gate stack of  claim 1  further comprising an interfacial layer located directly beneath said high-k gate dielectric, said interfacial layer comprises atoms of at least a semiconductor and oxygen. 
   
   
       3 . The multilayered gate stack of  claim 1  wherein said compositional ratio of metal to nitrogen is less than 1.08. 
   
   
       4 . The multilayered gate stack of  claim 1  wherein said metal of said metal nitrogen-containing layer is selected from Group IVB, VB, VIIB or VIIB of the Periodic Table of Elements. 
   
   
       5 . The multilayered gate stack of  claim 1  wherein said metal nitrogen-containing layer is TiN. 
   
   
       6 . The multilayered gate stack of  claim 1  wherein said Si-containing conductor is p-doped. 
   
   
       7 . The multilayered gate stack of  claim 1  wherein further comprising a metal silicide contact located directly on a surface of said Si-containing conductor. 
   
   
       8 . A semiconductor structure comprising:
 a semiconductor structure; and   at least one patterned multilayered gate stack located on a surface of said semiconductor structure, wherein said at least one patterned multilayered gate stack comprises a metal nitrogen-containing layer located on a surface of a high-k gate dielectric, said metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1, and a Si-containing conductor located directly on a surface of said metal nitrogen-containing layer.   
   
   
       9 . The semiconductor structure of  claim 8  further comprising an interfacial layer located directly beneath said high-k gate dielectric, said interfacial layer comprises atoms of at least a semiconductor and oxygen. 
   
   
       10 . The semiconductor structure of  claim 8  wherein said compositional ratio of metal to nitrogen is less than 1.08. 
   
   
       11 . The semiconductor structure of  claim 8  wherein said metal of said metal nitrogen-containing layer is selected from Group IVB, VB, VIIB or VIIB of the Periodic Table of Elements. 
   
   
       12 . The semiconductor structure of  claim 8  wherein said metal nitrogen-containing layer is TiN. 
   
   
       13 . The semiconductor structure of  claim 8  wherein said Si-containing conductor is p-doped. 
   
   
       14 . The semiconductor structure of  claim 8  wherein further comprising a metal silicide contact located directly on a surface of said Si-containing conductor.