Semiconductor chip having via electrodes and stacked semiconductor chips interconnected by the via electrodes

Abstract

A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

1 - 22 . (canceled) 
     
     
         22 . A method of forming a semiconductor device, comprising:
 forming a substrate;   forming a dielectric layer on the substrate;   forming a conductive pad on the dielectric layer;   forming a via trench through the conductive pad, the dielectric layer, and a portion of the substrate; and   forming a plurality of spike trenches through a bottom surface of the via trench and extending into the substrate, each of the spike trenches being spaced apart from each other; and   forming a via electrode by filling the spike trenches with a first conductive material and filling the via trench with a second conductive material.   
     
     
         23 . The method of  claim 22 , further comprising forming an insulation layer on the surfaces of the spike trenches and the via trench. 
     
     
         24 . The method of  claim 22 , wherein the first conductive material is the same as the second conductive material. 
     
     
         25 . The method of  claim 22 , wherein the first conductive material comprises one of W, Al, or polysilicon. 
     
     
         26 . The method of  claim 22 , further comprising lining the walls of the spike trenches and the via trench with a barrier metal prior to filling with the first conductive material and the second conductive material. 
     
     
         27 . The method of  claim 26 , wherein the barrier metal comprises one of, or a combination of, Ti, Ta, TiN or TaN. 
     
     
         28 . The method of  claim 22 , wherein the second conductive material is Cu. 
     
     
         29 . The method of  claim 22 , including forming a protrusion on the conductive pad by overfilling the via trench. 
     
     
         30 . The method of  claim 22 , further including exposing portions of the via electrode by removing portions of the substrate opposite the conductive pad. 
     
     
         31 . A method of forming a semiconductor device, comprising:
 forming a substrate;   forming a via trench into the substrate;   forming a plurality of spike trenches through a bottom surface of the via trench, further extending into the substrate, each of the spike trenches being spaced apart from each other;   forming a via electrode by filling the spike trenches and the via trench with a conductive material;   planarizing the top surface of the via electrode and the substrate;   forming a first dielectric layer on the planarized surface of the substrate and the via electrode;   forming an interconnection pattern in the first dielectric layer; and   forming a conductive pad on the first dielectric layer.   
     
     
         32 . The method of  claim 31 , further comprising forming an insulation layer on the surfaces of the spike trenches and the via trench 
     
     
         33 . The method of  claim 31 , further comprising a second dielectric layer including a circuit layer between the substrate and the first dielectric layer, and wherein the via electrode extends through the second dielectric layer. 
     
     
         34 . A method of forming a semiconductor device, comprising:
 forming a substrate;   forming a plurality of spike trenches in the substrate;   filling the spike trenches with a first conductive material;   forming a dielectric layer on the substrate;   forming a conductive pad on the dielectric layer;   forming a via trench through the conductive pad and the dielectric layer; and   filling the via trench with a second conductive material.   
     
     
         35 . The method of  claim 34 , further including forming a protrusion on the conductive pad by overfilling the via trench. 
     
     
         36 . The method of  claim 34 , wherein the first conductive material comprises one of W, Al, or polysilicon. 
     
     
         37 . The method of  claim 34 , wherein the second conductive material is Cu. 
     
     
         38 . A method of forming a semiconductor chip having a via electrode, comprising:
 providing a chip substrate having a chip front surface separated from a chip back surface;   forming a pair of via trenches between the chip front surface and the chip back surface, a first trench of the pair extending partially into the chip substrate, a second trench of the pair extending from the first trench further into the chip substrate, the first trench having a larger diameter than the second trench, and   filling the pair of via trenches with electrically conductive material to form the via electrode.   
     
     
         39 . The method of  claim 38 , further comprising:
 forming a dielectric layer on the chip front surface,   forming a conductive pad on the dielectric layer,   forming a protrusion on the conductive pad, the protrusion being electrically coupled to the via electrode.   
     
     
         40 . The method of  claim 39 , further comprising electrically coupling a redistribution circuit line to the protrusion such that via electrode is electrically connectable to other devices. 
     
     
         41 . The method of  claim 38 , wherein the pair of via trenches extend from the chip front surface to the chip back surface. 
     
     
         42 . The method of  claim 38 , wherein at least one of the pair of via trenches taper in diameter from the chip front surface toward the chip back surface. 
     
     
         43 . The method of  claim 38 , wherein forming the pair of via trenches comprises forming the second trench to have a plurality of trench spikes that extend from the first trench. 
     
     
         44 . The method of  claim 43 , wherein the trench spikes extend beyond the chip back surface. 
     
     
         45 . A method of stacking a pair of semiconductor chips having via electrodes, comprising:
 forming each of the pair of semiconductor chips by:
 providing a chip substrate having a chip front surface separated from a chip back surface; 
 forming a pair of via trenches between the chip front surface and the chip back surface, a first trench of the pair extending partially into the chip substrate, a second trench of the pair extending from the first trench further into the chip substrate, the first trench having a larger diameter than the second trench, the second trench having a plurality of trench spikes that extend from the first trench beyond the chip back surface, filling the pair of via trenches with electrically conductive material to provide a via electrode, 
 forming a dielectric layer on the chip front surface, 
 forming a conductive pad on the dielectric layer, 
 forming a protrusion on the conductive pad, the protrusion being electrically coupled to the via electrode, and 
 forming a conductive bump on the protrusion of one of the pair, 
   applying an adhesive on the dielectric layer and the conductive pad of the one of the pair for adhering the dielectric layer and the conductive pad of the one of the pair to the chip back surface of the other of the pair; and   pressing the pair of semiconductor chips together such that the spikes of the other of the pair penetrate the conductive bump of the one of the pair and the adhesive contacts the chip back surface of the other of the pair.   
     
     
         46 - 51 . (canceled)