US2010171156A1PendingUtilityA1

Method for Forming Semiconductor Contacts

Assignee: RAHHAL-ORABI NADIAPriority: Jun 26, 2007Filed: Mar 15, 2010Published: Jul 8, 2010
Est. expiryJun 26, 2027(~0.9 yrs left)· nominal 20-yr term from priority
H10W 20/089H10W 20/40H10W 20/082H10D 30/60
34
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Claims

Abstract

In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

Claims

exact text as granted — not AI-modified
1 . An apparatus comprising:
 a gate electrode including a top and a bottom, said top at a vertical level; and   a via that has an inclined slope that tapers down to the vertical level of the top of the gate electrode.   
   
   
       2 . The apparatus of  claim 1  wherein the via has vertical sides below the top of the gate electrode. 
   
   
       3 . The apparatus of  claim 1  including a dielectric layer, said gate electrode within said layer. 
   
   
       4 . The apparatus of  claim 3 , said via having a top surface aligned with the top surface of said layer. 
   
   
       5 . The apparatus of  claim 1  wherein said via tapers from said top surface to a narrower cross section at the top of the gate electrode. 
   
   
       6 . The apparatus of  claim 1  including a source and drain adjacent said gate. 
   
   
       7 . The apparatus of  claim 6 , said via making electrical contact to said source and drain through a lower portion of said via. 
   
   
       8 . A method comprising:
 forming a gate electrode over a substrate, said gate electrode having top and bottom surfaces;   forming a source and drain adjacent said gate electrode; and   forming a via that extends from one of said source and drain electrodes upwardly to the upper surface of said gate electrode and then continues upwardly, tapering outwardly.   
   
   
       9 . The method of  claim 8  including forming said via with vertical sides below the top surface of said gate electrode. 
   
   
       10 . The method of  claim 8  including forming a dielectric having an upper surface aligned with an upper surface of said via, said gate electrode being covered by said dielectric. 
   
   
       11 . The method of  claim 10  including aligning a top surface of the via with the upper surface of said layer.

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