Transistor Structure

Abstract

Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.

1 . A semiconductor device, comprising:
 a workpiece;   a channel region disposed within the workpiece;   a gate dielectric disposed over the channel region;   a gate disposed over the gate dielectric, the gate and the gate dielectric having sidewalls;   first, second and third sidewall spacers disposed adjacent the sidewalls of the gate, the third sidewall spacers comprising a stress-inducing material; and   a source region and a drain region disposed within the workpiece proximate the channel region, wherein the channel region, the gate dielectric, the gate, and the source and drain regions comprise a transistor, and wherein the sidewall spacers alter a performance of the transistor.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the third sidewall spacers comprising the stress-inducing material are spaced apart from the channel region of the workpiece by about 30 nm or less. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the transistor comprises a p channel metal oxide semiconductor (PMOS) field effect transistor (FET), wherein the third sidewall spacers comprising the stress-inducing material increase a compressive stress of the channel region, or wherein the transistor comprises an n channel metal oxide semiconductor (NMOS) FET, wherein the third sidewall spacers comprising the stress-inducing material increase a tensile stress of the channel region. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising an insulating material disposed between the sidewalls of the gate and the third sidewall spacer. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein the insulating material comprises an oxide material having a thickness of about 50 nm or less. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the workpiece comprises silicon, GaAs, InP or SiGe. 
     
     
         7 . The semiconductor device according to  claim 1  wherein the workpiece comprises a crystalline orientation of <1,1,0>. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the first sidewall spacers are oxide or nitride. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the second sidewall spacers are silicon oxide, silicon nitride and/or silicon oxy-nitride. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the stress-inducing material is a silicon nitride. 
     
     
         11 . A complementary metal oxide semiconductor (CMOS) device including the transistor of  claim 1 . 
     
     
         12 . A semiconductor device comprising:
 a first transistor having first source/drains, a first channel and a first gate, the first channel arranged beneath the first gate; and   a second transistor having second source/drains, a second channel and a second gate, the second channel being arranged beneath the second gate;   wherein the first transistor and the second transistor each comprises three sidewall spacers, and   wherein the first channel has a different stress than the second channel.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein first of the three sidewall spacers are an oxide or a nitride. 
     
     
         14 . The semiconductor device according to  claim 12 , wherein second of the three sidewall spacers are a silicon oxide, a silicon nitride and/or a silicon oxy-nitride. 
     
     
         15 . The semiconductor device according to  claim 12 , wherein third of the three sidewall spacers are a stress-inducing material. 
     
     
         16 . The semiconductor device according to  claim 12 , further comprising an insulating material disposed between second of the three sidewall spacers and third of the three sidewall spacers. 
     
     
         17 . The semiconductor device according to  claim 12 , wherein the first channel has a different crystalline orientation than the second channel. 
     
     
         18 . A CMOS transistor comprising:
 a PMOS transistor having first and second sidewall spacers, the first sidewall spacers comprising three layers and the second sidewall spacers comprising a stress-inducing material; and   a NMOS transistor having third and fourth sidewall spacers, the third sidewall spacers comprising the three layers and the fourth sidewall spacers comprising the stress-inducing material.   
     
     
         19 . The CMOS device according to  claim 18 , wherein the second sidewall spacers comprise the stress-inducing material increasing a compressive stress. 
     
     
         20 . The CMOS device according to  claim 18 , wherein the first and third sidewall spacers have a thickness of about 30 nm or less.