Bipolar Transistor, Band-Gap Reference Circuit and Virtual Ground Reference Circuit

Abstract

The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact.

1 . A bipolar transistor, comprising:
 a Silicon-On-Insulator wafer comprising a silicon substrate and a buried oxide layer and a top silicon layer sequentially on the silicon substrate;   a base area, an emitter area and a collector area in the top silicon layer, the base area being between the emitter area and the collector area, the conductivity type of the emitter area being the same as that of the collector area, and the conductivity type of the base area being opposite to those of the emitter area and the collector area;   a base area gate dielectric layer on the top silicon layer atop the base area;   a base area control-gate on the base area gate dielectric layer;   an emitter electrode connected to the emitter area via a first contact; and   a collector electrode connected to the collector area via a second contact,   wherein the bipolar transistor further comprises:   a base area control-gate electrode connected to the base area control-gate via a third contact.   
     
     
         2 . The bipolar transistor according to  claim 1 , further comprising a buffer area between the collector area and the base area, wherein the buffer area has the same doping type as that of the collector area but a lighter doping concentration than that of the collector area, and the interfaces between the buffer area and the collector area and between the emitter area and the base area are angled with respect to the surface of the semiconductor substrate. 
     
     
         3 . The bipolar transistor according to  claim 1 , wherein the base area control-gate is of polysilicon and has the opposite conductivity type to that of the base area. 
     
     
         4 . The bipolar transistor according to  claim 1 , further comprising an isolation layer on the top silicon layer on both sides of the base area gate dielectric layer and the base area control-gate. 
     
     
         5 . A method for fabricating a bipolar transistor according to  claim 1 , comprising:
 preparing a Silicon-On-Insulator wafer comprising a silicon substrate and a buried oxide layer and a top silicon layer sequentially on the silicon substrate;   forming an active area in the top silicon layer;   performing a first implantation in the active area;   patterning a base area in the active area and forming sequentially a base area gate dielectric layer and a base area control-gate on the top silicon layer and atop the base area;   performing a second implantation in the active area except the base area using ions of the opposite conductivity type to that of the first implantation to form an emitter area and a collector area;   forming a first interlayer dielectric layer on the top silicon layer to cover the base area gate dielectric layer and the base area control-gate;   forming a first contact, a second contact and a third contact in the first interlayer dielectric layer; and   forming a conductive layer on the first interlayer dielectric layer to form an emitter electrode connected to the emitter area via the first contact, a collector electrode connected to the collector area via the second contact, and a base area control-gate electrode connected to the base area control-gate via the third contact.   
     
     
         6 . The method for fabricating a bipolar transistor according to  claim 5 , further comprising performing additional implantations in the base area using ions of the same conductivity type as that of the first implantation. 
     
     
         7 . The method for fabricating a bipolar transistor according to  claim 5 , further comprising performing a third implantation in the active area except the base area using ions of the same conductivity type as that of the second implantation in an angled direction with respect to the surface of the semiconductor substrate to form a buffer area connecting the base area and the collector area after performing the second implantation and before forming the first interlayer dielectric layer. 
     
     
         8 . The method for fabricating a bipolar transistor according to  claim 7 , wherein the base area control-gate is of polysilicon, and the method further comprises the step of doping the base area control-gate so that the conductivity type of the doped base area control-gate is opposite to that of the base area. 
     
     
         9 . A method for turning on the bipolar transistor according to  claim 1 , comprising:
 applying a first voltage to the base area control-gate electrode;   applying a second voltage to the collector electrode; and   applying a third voltage to the emitter electrode,   wherein minority carriers are formed on the surface of the collector area due to the electric field resulting from the base area control-gate voltage, the minority carriers are of the same type as majority carriers in the base area and flow into the base area to form a gate-induced drain leakage current, and the gate-induced drain leakage current continuously flow into the emitter area to forward bias the PN junction between the base area and the emitter area.   
     
     
         10 . The method for turning on the bipolar transistor according to  claim 9 , wherein the conductivity type of the base area is the p-type, the conductivity types of the collector area and the emitter area are the n-type, and the first voltage applied to the base area control-gate electrode is below the second voltage applied to the collector electrode, and the third voltage applied to the emitter electrode is below the first voltage. 
     
     
         11 . The method for turning on the bipolar transistor according to  claim 9 , wherein the base area is the n-type, the collector area and the emitter area are the p-type, and the first voltage applied to the base area control-gate electrode is above the second voltage applied to the collector electrode, and the third voltage applied to the emitter electrode is above the second voltage. 
     
     
         12 . A band-gap reference source circuit with the bipolar transistor according to  claim 1 , comprising:
 a first terminal and a second terminal with a first voltage difference;   a first current source with one terminal electrically connected to the first terminal;   a first bipolar transistor with an emitter electrode connected to the other terminal of the first current source;   a first load with one terminal electrically connected to a collector electrode of the first bipolar transistor and the other terminal electrically connected to the second terminal;   a third terminal and a fourth terminal with a second voltage difference;   a second current source with one terminal electrically connected to the third terminal;   a second bipolar transistor with an emitter electrode connected to the other terminal of the second current source;   a second load with one terminal electrically connected to a collector electrode of the second bipolar transistor and the other terminal electrically connected to the fourth terminal;   wherein a base area control-gate electrode of the first bipolar transistor and a base area control-gate electrode of the second bipolar transistor are connected to output of the band-gap reference source circuit; and   a control unit with a first input electrically connected to the emitter electrode of the first bipolar transistor, a second input electrically connected to the emitter electrode of the second bipolar transistor, and an output electrically connected to the output of the band-gap reference source circuit, wherein the control unit is adapted to adjust dynamically an output voltage to make both currents at the emitter electrode and the collector electrode of the first bipolar transistor to be the same as the current output from the first current source, to make both currents at the emitter electrode and the collector electrode of the second bipolar transistor to be the same as the current output from the second current source, and to make a temperature coefficient of the output voltage of the band-gap reference source circuit nearly zero by selecting magnitudes of the first voltage difference, the second voltage difference, the output current of the first current source, the output current of the second current source, the first load and the second load.   
     
     
         13 . The band-gap reference source circuit according to  claim 12 , wherein the first bipolar transistor is in the same structure and size as those of the second bipolar transistor, the first voltage difference is the same as the second voltage difference, the first load is a first resistor and a second resistor, and the second load is the second resistor. 
     
     
         14 . The band-gap reference source circuit according to  claim 13 , wherein both the first bipolar transistor and the second bipolar transistor are of the NPN type, the first terminal and the third terminal are grounded, and the second terminal and the fourth terminal are connected to an external voltage source. 
     
     
         15 . The band-gap reference source circuit according to  claim 13 , wherein both the first bipolar transistor and the second bipolar transistor are of the PNP type, the first terminal and the third terminal are connected to an external voltage source, and the second terminal and the fourth terminal are grounded. 
     
     
         16 . A bipolar transistor, comprising:
 a Silicon-On-Insulator wafer comprising a silicon substrate and a buried oxide layer and a top silicon layer sequentially on the silicon substrate;   a base area, an emitter area and a collector area in the top silicon layer, the base area being between the emitter area and the collector area, the conductivity type of the emitter area being the same as that of the collector area, and the conductivity type of the base area being opposite to those of the emitter area and the collector area;   a base area gate dielectric layer on the top silicon layer and atop the base area;   a polysilicon layer on the base area gate dielectric layer;   an emitter electrode connected to the emitter area via a first contact; and   a collector electrode connected to the collector area via a second contact,   wherein the bipolar transistor further comprises:   a base area control-gate electrode connected to the polysilicon layer via a third contact, the conductivity type of the polysilicon layer being the same as that of the base area and opposite to those of the emitter area and the collector area.   
     
     
         17 . The bipolar transistor according to  claim 16 , further comprising a buffer area between the collector area and the base area, wherein the buffer area has the same doping type as that of the collector area but a lighter doping concentration than that of the collector area, and the interfaces between the buffer area and the collector area and between the emitter area and the base area are angled with respect to the surface of the semiconductor substrate. 
     
     
         18 . The bipolar transistor according to  claim 16 , wherein the doping concentrations of the polysilicon layers of a first bipolar transistor and a second bipolar transistor range from 10 19  cm −3  to 10 22  cm −3 . 
     
     
         19 . A method for fabricating a bipolar transistor according to  claim 16 , comprising:
 preparing a Silicon-On-Insulator wafer comprising a silicon substrate and a buried oxide layer and a top silicon layer sequentially on the silicon substrate;   forming an active area in the top silicon layer;   performing a first implantation in the active area;   patterning a base area in the active area and forming sequentially a base area gate dielectric layer and a polysilicon layer on the top silicon layer and atop the base area;   performing a fourth implantation in the polysilicon layer to make the conductivity type of the polysilicon layer the same as that of the base area;   performing a second implantation in the active area except the base area using ions of the opposite conductivity type to that of the first implantation to form an emitter area and a collector area;   forming a first interlayer dielectric layer on the top silicon layer to cover the base area gate dielectric layer and the polysilicon layer;   forming a first contact, a second contact and a third contact in the first interlayer dielectric layer; and   forming a conductive layer on the first interlayer dielectric layer to form an emitter electrode connected to the emitter area via the first contact, a collector electrode connected to the collector area via the second contact, and a base area control-gate electrode connected to the polysilicon layer via the third contact.   
     
     
         20 . The method for fabricating a bipolar transistor according to  claim 19 , further comprising performing additional implantations in the base area using ions of the same conductivity type as that of the first implantation. 
     
     
         21 . The method for fabricating a bipolar transistor according to  claim 19 , further comprising performing a third implantation in the active area except the base area using ions of the same conductivity type as that of the second implantation in an angled direction with respect to the surface of the semiconductor substrate to form a buffer area connecting the base area and the collector area after performing the second implantation and before forming the first interlayer dielectric layer. 
     
     
         22 . A method for turning on the bipolar transistor according to  claim 16 , comprising:
 applying a first voltage to the base area control-gate electrode;   applying a second voltage to the collector electrode; and   applying a third voltage to the emitter electrode,   wherein minority carriers are attracted on the surface of the collector area due to the electric field resulting from the base area control-gate voltage, the minority carriers are of the same type as majority carriers in the base area and flow into the base area to form a gate-induced drain leakage current, and the gate-induced drain leakage current continuously flow into the emitter area to forward bias the PN junction between the base area and the emitter area.   
     
     
         23 . The method for triggering the bipolar transistor according to  claim 22 , wherein the conductivity type of the base area is the p-type, the conductivity types of the collector area and the emitter area are the n-type, and the first voltage applied to the base area control-gate electrode is below the second voltage applied to the collector electrode, and the third voltage applied to the emitter electrode is below the first voltage. 
     
     
         24 . The method for triggering the bipolar transistor according to  claim 22 , wherein the conductivity type of the base area is the n-type, the conductivity types of the collector area and the emitter area are the p-type, and the first voltage applied to the base area control-gate electrode is above the second voltage applied to the collector electrode, and the third voltage applied to the emitter electrode is above the second voltage. 
     
     
         25 . A virtual ground reference circuit with a bipolar transistor according to  claim 16 , comprising:
 a first terminal and a second terminal with a first voltage difference;   a first current source with one terminal electrically connected to the first terminal;   a first bipolar transistor with an emitter electrode connected to the other terminal of the first current source;   a first load with one terminal electrically connected to a collector electrode of the first bipolar transistor and the other terminal electrically connected to the second terminal;   a third terminal and a fourth terminal with a second voltage difference;   a second current source with one terminal electrically connected to the third terminal;   a second bipolar transistor with an emitter electrode connected to the other terminal of the second current source;   a second load with one terminal electrically connected to a collector electrode of the second bipolar transistor and the other terminal electrically connected to the fourth terminal;   wherein a base area control-gate electrode of the first bipolar transistor and a base area control-gate electrode of the second bipolar transistor are connected to an output of the virtual ground reference circuit, and both the first bipolar transistor and the second bipolar transistor are of the PNP type; and   a control unit with a first input electrically connected to the emitter electrode of the first bipolar transistor, a second input electrically connected to the emitter electrode of the second bipolar transistor, and an output electrically connected to the output of the virtual ground reference circuit; wherein the control unit is adapted to make both currents at the emitter electrode and the collector electrode of the first bipolar transistor to be the same as the current output from the first current source, to make both currents at the emitter electrode and the collector electrode of the second bipolar transistor to be the same as the current output from the second current source, and to make a temperature coefficient of an output voltage of the virtual ground reference circuit nearly zero by selecting magnitudes of the current output of the first current source, the output current of the second current source, the first load and the second load.   
     
     
         26 . The virtual ground reference circuit according to  claim 25 , wherein the first bipolar transistor is in the same structure as that of the second bipolar transistor, the first voltage difference is the same as the second voltage difference, the first load is a first resistor and a second resistor, and the second load is the second resistor. 
     
     
         27 . The virtual ground reference circuit according to  claim 26 , wherein the first terminal and the third terminal are connected to an external voltage source, and the second terminal and the fourth terminal are grounded. 
     
     
         28 . The virtual ground reference circuit according to  claim 26 , wherein the doping concentrations of the polysilicon layers of the first bipolar transistor and the second bipolar transistor are the same. 
     
     
         29 . A double band-gap voltage circuit with a bipolar transistor according to  claim 16 , comprising:
 a first terminal and a second terminal with a first voltage difference;   a first current source with one terminal electrically connected to the first terminal;   a first bipolar transistor with an emitter electrode connected to the other terminal of the first current source;   a first load with one terminal electrically connected to a collector electrode of the first bipolar transistor and the other terminal electrically connected to the second terminal;   a third terminal and a fourth terminal with a second voltage difference;   a second current source with one terminal electrically connected to the third terminal;   a second bipolar transistor with an emitter electrode connected to the other terminal of the second current source;   a second load with one terminal electrically connected to a collector electrode of the second bipolar transistor and the other terminal electrically connected to the fourth terminal;   wherein a base area control-gate electrode of the first bipolar transistor and a base area control-gate electrode of the second bipolar transistor are connected to an output of the double band-gap voltage circuit, and both the first bipolar transistor and the second bipolar transistor are of the NPN type; and   a control unit with a first input electrically connected to the emitter electrode of the first bipolar transistor, a second input electrically connected to the emitter electrode of the second bipolar transistor, and an output electrically connected to the output of the double band-gap voltage circuit; wherein the control unit is adapted to make both currents at the emitter electrode and the collector electrode of the first bipolar transistor to be the same as the current output from the first current source, to make both currents at the emitter electrode and the collector electrode of the second bipolar transistor to be the same as the current output from the second current source, and to make a temperature coefficient of an output voltage of the double band-gap voltage circuit be zero and the output voltage of the double band-gap voltage circuit be twice a silicon band-gap by selecting magnitudes of the output current of the first current source, the output current of the second current source, the first load and the second load.   
     
     
         30 . The double band-gap voltage circuit according to  claim 29 , wherein the first bipolar transistor is in the same structure as that of the second bipolar transistor, the first voltage difference is the same as the second voltage difference, the first load is a first resistor and a second resistor, and the second load is the second resistor. 
     
     
         31 . The double band-gap voltage circuit according to  claim 30 , wherein the first terminal and the third terminal are grounded, and the second terminal and the fourth terminal are connected to an external voltage source. 
     
     
         32 . The double band-gap voltage circuit according to  claim 30 , wherein the doping concentrations of polysilicon layers of the first bipolar transistor and the second bipolar transistor are the same. 
     
     
         33 . The method for fabricating a bipolar transistor according to  claim 6 , further comprising performing a third implantation in the active area except the base area using ions of the same conductivity type as that of the second implantation in an angled direction with respect to the surface of the semiconductor substrate to form a buffer area connecting the base area and the collector area after performing the second implantation and before forming the first interlayer dielectric layer. 
     
     
         34 . The bipolar transistor according to  claim 17 , wherein the doping concentrations of the polysilicon layers of a first bipolar transistor and a second bipolar transistor range from 10 19  cm −3  to 10 22  cm −3 . 
     
     
         35 . The method for fabricating a bipolar transistor according to  claim 20 , further comprising performing a third implantation in the active area except the base area using ions of the same conductivity type as that of the second implantation in an angled direction with respect to the surface of the semiconductor substrate to form a buffer area connecting the base area and the collector area after performing the second implantation and before forming the first interlayer dielectric layer.