US2011101470A1PendingUtilityA1

High-k metal gate electrode structures formed by separate removal of placeholder materials in transistors of different conductivity type

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Assignee: HEMPEL KLAUSPriority: Oct 30, 2009Filed: Sep 30, 2010Published: May 5, 2011
Est. expiryOct 30, 2029(~3.3 yrs left)· nominal 20-yr term from priority
H10D 64/01304H10D 64/01318H10D 30/601H10D 84/0179H10D 84/0177H10D 84/0167H10D 84/038H10D 64/017H10D 30/792H10D 30/0225
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Claims

Abstract

In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Claims

exact text as granted — not AI-modified
1 . A method, comprising:
 forming a first portion of an opening in a gate electrode structure of a transistor by removing a first portion of a placeholder electrode material of said gate electrode structure, said first portion of said opening having a width at a top area of said opening;   increasing said width of said first portion of said opening at a top area thereof in the presence of a second portion of said placeholder electrode material;   removing said second portion of said placeholder electrode material;   forming a material layer in said opening having said increased width at the top area thereof, said material layer comprising a work function adjusting species; and   filling said opening with a conductive electrode material.   
     
     
         2 . The method of  claim 1 , wherein increasing a width of said first portion of said opening comprises performing a plasma assisted etch process. 
     
     
         3 . The method of  claim 2 , wherein forming a first portion of said opening comprises performing said plasma assisted etch process so as to remove said first portion of said placeholder electrode material and to round corners of said opening. 
     
     
         4 . The method of  claim 2 , wherein removing said first portion of said placeholder electrode material comprises performing a first wet chemical etch process. 
     
     
         5 . The method of  claim 1 , wherein removing said second portion of said placeholder electrode material comprises performing a wet chemical etch process. 
     
     
         6 . The method of  claim 5 , wherein performing said wet chemical etch process comprises using a conductive cap layer formed above a gate dielectric material as an etch stop material. 
     
     
         7 . The method of  claim 1 , wherein filling a conductive electrode material into said opening comprises depositing said conductive electrode material so as to overfill said opening and removing excess material by performing at least one of an etch process and a polishing process. 
     
     
         8 . The method of  claim 7 , wherein removing excess material comprises removing material of said conductive electrode material and a portion of a dielectric material laterally delineating said opening so as to adjust a height of said gate electrode structure. 
     
     
         9 . The method of  claim 1 , further comprising forming a high-k dielectric material at least at the bottom of said opening prior to filling said conductive electrode material into said opening. 
     
     
         10 . The method of  claim 1 , further comprising forming a high-k dielectric material of said gate electrode structure prior to forming said opening. 
     
     
         11 . The method of  claim 1 , further comprising performing a cleaning process on said second portion of said placeholder electrode material after increasing said width. 
     
     
         12 . A method, comprising:
 removing a first portion of a placeholder electrode material of a gate electrode structure of a transistor, said placeholder electrode material being laterally enclosed by an insulating material;   rounding corner areas of said insulating material in the presence of a second portion of said placeholder electrode material;   removing said second portion by performing a wet chemical etch process so as to form an opening after rounding said corner areas; and   forming a gate electrode in said opening.   
     
     
         13 . The method of  claim 12 , wherein rounding said corner areas comprises performing a plasma assisted etch process. 
     
     
         14 . The method of  claim 12 , wherein rounding said corner areas comprises performing a particle bombardment. 
     
     
         15 . The method of  claim 14 , wherein performing said particle bombardment comprises performing an ion sputtering process. 
     
     
         16 . The method of  claim 12 , further comprising performing a cleaning process on an exposed surface of said second portion prior to performing said wet chemical etch process. 
     
     
         17 . The method of  claim 12 , wherein removing said first portion of said placeholder electrode material comprises performing a first wet chemical etch process. 
     
     
         18 . The method of  claim 12 , wherein removing said first portion of said placeholder electrode material comprises performing a plasma based etch process. 
     
     
         19 . The method of  claim 18 , wherein performing said plasma based etch process comprises adapting at least one process parameter of said plasma based etch process so as to control a degree of material erosion at said corner areas. 
     
     
         20 . A semiconductor device, comprising:
 a gate electrode structure of a transistor formed above a semiconductor region, said gate electrode structure comprising a gate insulation layer including a high-k dielectric material and an electrode material formed on said gate insulation layer and having a tapered cross-sectional configuration, said gate electrode structure further comprising a work function adjusting material layer formed on sidewalls of said electrode material, a thickness of said work function adjusting material layer having a variation of less than 10 percent along said sidewalls.   
     
     
         21 . The semiconductor device of  claim 20 , wherein a length of said electrode material at said gate insulation layer is approximately 30 nm or less. 
     
     
         22 . The semiconductor device of  claim 20 , wherein said work function adjusting material layer comprises at least one of titanium and tantalum.

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