Inventor · disambiguated record
Markus Lenski
Also filed as: LENSKI MARKUS · LENSKI MARKUS E
58 granted patents·6 pending applications·717 citations·filing 2003–2018
98Inventor score
Files withGLOBALFOUNDRIES INC25ADVANCED MICRO DEVICES INC10KRONHOLZ STEPHAN8LENSKI MARKUS5MOWRY ANTHONY4
Top patents by PatentIndex Score
64 records- 0197US10483154B1Front-end-of-line device structure and method of forming such a front-end-of-line device structureGLOBALFOUNDRIES INC·Filed 2018·Granted Nov 19, 2019·399 cites·19 claims
- 0294US7741663B2Air gap spacer formationGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 22, 2010·57 cites·20 claims
- 0394US7354838B2Technique for forming a contact insulation layer with enhanced stress transfer efficiencyADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 8, 2008·28 cites·19 claims
- 0493US7208397B2Transistor having an asymmetric source/drain and halo implantation region and a method of forming the sameADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 24, 2007·23 cites·19 claims
- 0592US8071442B2Transistor with embedded Si/Ge material having reduced offset to the channel regionKRONHOLZ STEPHAN·Filed 2009·Granted Dec 6, 2011·22 cites·17 claims
- 0692US7943462B1Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacerGLOBALFOUNDRIES INC·Filed 2010·Granted May 17, 2011·14 cites·20 claims
- 0792US7754556B2Reducing transistor junction capacitance by recessing drain and source regionsADVANCED MICRO DEVICES INC·Filed 2008·Granted Jul 13, 2010·18 cites·19 claims
- 0891US7763505B2Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientationsGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 27, 2010·18 cites·16 claims
- 0988US7981740B2Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterningGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 19, 2011·13 cites·21 claims
- 1086US8349694B2Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloyGLOBALFOUNDRIES INC·Filed 2010·Granted Jan 8, 2013·9 cites·18 claims
- 1186US8227266B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsMOWRY ANTHONY·Filed 2010·Granted Jul 24, 2012·6 cites·7 claims
- 1285US8367495B2Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric materialGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 5, 2013·8 cites·20 claims
- 1384US8298894B2Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layerLENSKI MARKUS·Filed 2010·Granted Oct 30, 2012·8 cites·12 claims
- 1483US7713763B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsADVANCED MICRO DEVICES INC·Filed 2008·Granted May 11, 2010·6 cites·11 claims
- 1582US8357573B2Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrodeGLOBALFOUNDRIES INC·Filed 2010·Granted Jan 22, 2013·5 cites·15 claims
- 1678US8440559B2Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layerGLOBALFOUNDRIES INC·Filed 2012·Granted May 14, 2013·4 cites·20 claims
- 1778US8383500B2Semiconductor device formed by a replacement gate approach based on an early work function metalGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 26, 2013·5 cites·20 claims
- 1876US8815674B1Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regionsGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 26, 2014·5 cites·13 claims
- 1975US8765542B1Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regionsGLOBALFOUNDARIES INC·Filed 2013·Granted Jul 1, 2014·4 cites·16 claims
- 2075US8765559B2Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor materialKRONHOLZ STEPHAN·Filed 2012·Granted Jul 1, 2014·4 cites·20 claims
- 2174US8652917B2Superior stability of characteristics of transistors having an early formed high-K metal gateLENSKI MARKUS·Filed 2012·Granted Feb 18, 2014·4 cites·20 claims
- 2274US8173501B2Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy depositionKRONHOLZ STEPHAN·Filed 2010·Granted May 8, 2012·3 cites·16 claims
- 2373US7754555B2Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrodeGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 13, 2010·5 cites·8 claims
- 2473US7745334B2Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniquesADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 29, 2010·4 cites·17 claims
- 2571US8198166B2Using high-k dielectrics as highly selective etch stop materials in semiconductor devicesKAMMLER THORSTEN·Filed 2010·Granted Jun 12, 2012·3 cites·17 claims
- 2671US7879667B2Blocking pre-amorphization of a gate electrode of a transistorGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 1, 2011·3 cites·29 claims
- 2771US7344984B2Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistorsADVANCED MICRO DEVICES INC·Filed 2006·Granted Mar 18, 2008·4 cites·21 claims
- 2871US7316975B2Method of forming sidewall spacersADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 8, 2008·5 cites·18 claims
- 2969US8735270B2Method for making high-K metal gate electrode structures by separate removal of placeholder materialsGLOBALFOUNDRIES INC·Filed 2013·Granted May 27, 2014·2 cites·20 claims
- 3068US8871586B2Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor materialGLOBALFOUNDRIES INC·Filed 2012·Granted Oct 28, 2014·2 cites·35 claims
- 3166US7906385B2Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography stepsGLOBALFOUNDRIES INC·Filed 2008·Granted Mar 15, 2011·3 cites·6 claims
- 3265US8969916B2Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrodeGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 3, 2015·1 cites·20 claims
- 3365US8835209B2Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areasKRONHOLZ STEPHAN·Filed 2012·Granted Sep 16, 2014·2 cites·24 claims
- 3464US7528026B2Method for reducing silicide defects by removing contaminants prior to drain/source activationADVANCED MICRO DEVICES INC·Filed 2006·Granted May 5, 2009·2 cites·16 claims
- 3564US7109086B2Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition techniqueADVANCED MICRO DEVICES INC·Filed 2004·Granted Sep 19, 2006·11 cites·27 claims
- 3663US7745337B2Method of optimizing sidewall spacer size for silicide proximity with in-situ cleanGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 29, 2010·2 cites·26 claims
- 3761US9646838B2Method of forming a semiconductor structure including silicided and non-silicided circuit elementsGLOBALFOUNDRIES INC·Filed 2014·Granted May 9, 2017·1 cites·27 claims
- 3858US8564120B2Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backsideMOWRY ANTHONY·Filed 2009·Granted Oct 22, 2013·1 cites·20 claims
- 3954US8847205B2Spacer for a gate electrode having tensile stress and a method of forming the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 30, 2014·0 cites·21 claims
- 4054US8530894B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsMOWRY ANTHONY·Filed 2012·Granted Sep 10, 2013·0 cites·7 claims
- 4153US8847404B2Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional moleculesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 30, 2014·0 cites·14 claims
- 4251US8557667B2Spacer for a gate electrode having tensile stress and a method of forming the sameRUELKE HARTMUT·Filed 2004·Granted Oct 15, 2013·3 cites·15 claims
- 4348US8440561B2Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional moleculesKRONHOLZ STEPHAN·Filed 2010·Granted May 14, 2013·0 cites·13 claims
- 4447US8828819B2Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrodeGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 9, 2014·0 cites·21 claims
- 4547US7977179B2Dopant profile tuning for MOS devices by adapting a spacer width prior to implantationGLOBALFOUNDRIES INC·Filed 2008·Granted Jul 12, 2011·0 cites·7 claims
- 4644US8183605B2Reducing transistor junction capacitance by recessing drain and source regionsFEUDEL THOMAS·Filed 2010·Granted May 22, 2012·0 cites·24 claims
- 4742US8507351B2Dopant profile tuning for MOS devices by adapting a spacer width prior to implantationMOWRY ANTHONY·Filed 2011·Granted Aug 13, 2013·0 cites·17 claims
- 4842US2011101470A1High-k metal gate electrode structures formed by separate removal of placeholder materials in transistors of different conductivity typeHEMPEL KLAUS·Filed 2010·Application pending·0 cites
- 4941US8987144B2High-K metal gate electrode structures formed by cap layer removal without sacrificial spacerKRONHOLZ STEPHAN·Filed 2011·Granted Mar 24, 2015·0 cites·15 claims
- 5041US8324108B2Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistryRICHTER RALF·Filed 2011·Granted Dec 4, 2012·0 cites·20 claims
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