Fabrication method of semiconductor integrated circuit device

Abstract

To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

1 . An integrated circuit device comprising:
 a first Intellectual Property module and a second Intellectual Property module formed on a chip;   a first pad formed on the chip and electrically connected to the first Intellectual Property module;   a second pad formed on the chip and electrically connected to the second Intellectual Property module; and   a first test pad formed on the chip and exclusively used for probe testing the first IP module,   wherein the first test pad is arranged on the chip such that a distance between the first test pad and the first Intellectual Property module is smaller than a distance between the first pad and the first Intellectual Property module.   
     
     
         2 . The integrated circuit device according to  claim 1 , wherein the first Intellectual Property module includes a Built In Self Test circuit electrically connected to the first test pad. 
     
     
         3 . The integrated circuit device according to  claim 1 , further comprising:
 a second test pad formed on the chip and exclusively used for probe testing the second Intellectual Property module,   wherein the second test pad is arranged on the chip such that a distance between the second test pad and the second Intellectual Property module is smaller than a distance between the second pad and the second Intellectual Property module.   
     
     
         4 . The integrated circuit device according to  claim 3 ,
 wherein the first Intellectual Property module includes a Built In Self Test circuit electrically connected to the first test pad, and   wherein the second Intellectual Property module includes a Built In Self Test circuit electrically connected to the second test pad.   
     
     
         5 . The integrated circuit device according to  claim 1 , wherein a signal for test applied to the first test pad is inputted into the first Intellectual Property module and without going through the second Intellectual Property module. 
     
     
         6 . The integrated circuit device according to  claim 3 , wherein a first signal for test applied to the first test pad is inputted into the first Intellectual Property module and without going through the second Intellectual Property module,
 wherein a second signal for test applied to the second test pad is inputted into the second Intellectual Property module and without going through the first Intellectual Property module.   
     
     
         7 . An integrated circuit device comprising:
 a first Intellectual Property module and a second Intellectual Property module formed on a chip;   a first pad formed on the chip and electrically connected to the first Intellectual Property module;   a second pad formed on the chip and electrically connected to the second Intellectual Property module;   a first test pad formed on the chip and exclusively used for probe testing the first Intellectual Property module; and   a second test pad formed on the chip and exclusively used for probe testing the second Intellectual Property module,   wherein a first signal for test applied to the first test pad is inputted into the first Intellectual Property module and without going through the second Intellectual Property module,   wherein a second signal for test applied to the second test pad is inputted into the second Intellectual Property module and without going through the first Intellectual Property module.   
     
     
         8 . The integrated circuit device according to  claim 7 ,
 wherein the first Intellectual Property module includes a Built In Self Test circuit electrically connected to the first test pad, and   wherein the second Intellectual Property module includes a Built In Self Test circuit electrically connected to the second test pad.