Semiconductor device and method of manufacturing same

Abstract

A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate having a first region including a memory cell and a second region including a logic circuit;   a first insulating layer formed on said semiconductor substrate;   first and second contact plugs including a first high-melting metal, and formed in said first insulating layer to be electrically connected to said semiconductor substrate, in said first region and whose upper surfaces are exposed from said first insulating layer;   a second insulating layer formed over said first insulating layer;   a capacitor having an electrode including a second high-melting metal, and formed in said second insulating layer to be electrically connected to said first contact plug;   a third insulating layer formed over said second insulating layer;   a first copper wiring having a first copper interconnection and a first barrier metal layer on a side surface and on a lower surface of said first copper interconnection, and formed in said third insulating layer in said first region;   a second copper wiring having a second copper interconnection and a second barrier metal layer on a side surface and on a lower surface of said second copper interconnection, and formed in said third insulating layer; and   a plurality of conducting contacts including a third high-melting metal, formed in said first insulating layer, said second insulating layer and said third insulating layer, said plurality of conducting contacts electrically connected to both said second copper wiring and said semiconductor substrate.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein at least one of said plurality of conducting contacts is a third contact plug formed in a region including said second insulating layer. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein said plurality of conducting contacts includes a first conducting contact formed in said first insulating layer and a second conducting contact formed in a region including said second insulating layer, and
 wherein said first conducting contact is electrically connected to both said second conducting contact and said semiconductor substrate.