Method and apparatus for a zero voltage processor sleep state

Abstract

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of cores, wherein each of the plurality of cores include,
 one or more execution units, 
 a plurality of caches, and 
 a power management logic to cause the processor to,
 enter a low power state in which a clock signal provided to the one or more execution units is gated, wherein the power management logic to further cause the clock signal provided to the processor to be gated in response to executing a power-save instruction, 
 enter a sleep state in which the frequency of the clock signal and a voltage provided to the one or more execution units is reduced in response to determining that a low power mode is to be entered. 
 
   
     
     
         2 . The processor of  claim 1 , wherein the processor to consume a lower power in the sleep state compared to that of the low power state. 
     
     
         3 . The processor of  claim 1 , wherein the power-save instruction may include a MWAIT instruction. 
     
     
         4 . The processor of  claim 1 , wherein each of the plurality of cores may process the power-save instruction. 
     
     
         5 . The processor of  claim 1 , wherein the voltage provided to the one or more execution units includes a zero voltage state. 
     
     
         6 . The processor of  claim 1 , wherein the power management logic to cause the processor to enter the low power state first and then enter the sleep state. 
     
     
         7 . The processor of  claim 1 , wherein the power management logic to cause the processor to enter the sleep state directly from an active state without entering the low power state. 
     
     
         8 . The processor of  claim 1 , wherein the power management logic to cause the processor to enter the low power state in response to an operating system processing the power-save instruction.