Variable resistance memory

Abstract

A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

1 .- 18 . (canceled) 
     
     
         19 . A variable resistance memory, comprising:
 a lower electrode on a semiconductor substrate;   a data storage pattern formed on the lower electrode; and   a hard mask pattern formed on the data storage pattern, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern.   
     
     
         20 . The variable resistance memory as claimed in  claim 19 , wherein the width of the hard mask pattern narrows gradually from the bottom surface to the top surface. 
     
     
         21 . The variable resistance memory as claimed in  claim 19 , wherein an angle of inclination between the sidewall of the hard mask pattern and the bottom surface of the hard mask pattern is about  30  degrees to about  60  degrees. 
     
     
         22 . The variable resistance memory as claimed in  claim 19 , wherein the data storage pattern includes at least one of materials having a variable resistance property. 
     
     
         23 . The variable resistance memory as claimed in  claim 19 , further comprising a capping layer on a sidewall of the hard mask pattern. 
     
     
         24 . The variable resistance memory as claimed in  claim 23 , wherein the capping layer includes an insulation material capable of preventing oxygen diffusion. 
     
     
         25 . The variable resistance memory as claimed in  claim 23 , wherein a difference between a thickness of a portion of the capping layer on a sidewall of the hard mask pattern and a thickness of a portion of the capping layer on a sidewall of the data storage pattern is about 25% of the thickness of the portion of the capping layer on the sidewall of the hard mask pattern or less, the thickness being measured along a direction parallel to a line connecting two adjacent hard mask patterns. 
     
     
         26 . The variable resistance memory as claimed in  claim 23 , further comprising an upper electrode between the hard mask pattern and the data storage pattern. 
     
     
         27 . The variable resistance memory as claimed in  claim 26 , the capping layer extends to sidewalls of the data storage pattern and the upper electrode. 
     
     
         28 . The variable resistance memory as claimed in  claim 27 , wherein a thickness of the capping layer on sidewalls of the hard mask pattern, data storage pattern, and upper electrode is substantially uniform, the thickness being measured along a direction parallel to a line connecting two adjacent hard mask patterns. 
     
     
         29 . The variable resistance memory as claimed in  claim 26 , wherein the data storage pattern, the upper electrode, and the lower surface of the hard mask pattern have the same width. 
     
     
         30 . The variable resistance memory as claimed in  claim 23 , wherein the lowest point of a bottom surface of the capping layer is lower than a bottom surface of the data storage pattern. 
     
     
         31 . The variable resistance memory as claimed in  claim 19 , wherein the variable resistance memory comprises a plurality of memory structures disposed in parallel to each other, and each of the memory structures includes the data storage pattern and the hard mask pattern. 
     
     
         32 . The variable resistance memory as claimed in  claim 31 , further comprising a capping layer conformally covering surfaces of the plurality of memory structures. 
     
     
         33 . The variable resistance memory as claimed in  claim 19 , wherein the variable resistance memory comprises a plurality of memory structures are disposed on a dielectric layer having a recessed portion between adjacent the memory structures, and an top surface of the recessed portion is lower than a bottom surface of the data storage pattern. 
     
     
         34 . The variable resistance memory as claimed in  claim 33 , further comprising a capping layer conformally covering surfaces of the memory structures and the recessed portion of the dielectric layer.