US2012205623A1PendingUtilityA1

NON-POLAR (Al,B,In,Ga)N QUANTUM WELL AND HETEROSTRUCTURE MATERIALS AND DEVICES

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Individually held — no corporate assignee on recordPriority: Apr 15, 2002Filed: Apr 26, 2012Published: Aug 16, 2012
Est. expiryApr 15, 2022(expired)· nominal 20-yr term from priority
Inventors:Michael D. CravenStacia KellerSteven P. DenbaarsTal MargalithJames S. SpeckShuji NakamuraUmesh Mishra
H10P 14/3466H10P 14/3416H10P 14/3216H10P 14/2926H10P 14/2921H10P 14/2901H10P 14/276H10P 14/271H10P 14/24C30B 25/04C30B 29/605C30B 25/105C30B 25/02C30B 29/403C30B 29/406C30B 25/18
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Claims

Abstract

A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 2 0) a-plane GaN layers are grown on an r-plane (11 0 2) sapphire substrate using MOCVD. These non-polar (11 2 0) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Claims

exact text as granted — not AI-modified
1 . A nitride semiconductor device, comprising:
 one or more non-polar Group III nitride layers grown on or above a non-polar surface of a Gallium Nitride (GaN) substrate, wherein the non-polar surface of the GaN substrate is a grown surface.   
     
     
         2 . The device of  claim 1 , wherein the non-polar Group III nitride layers comprise one or more non-polar Group III nitride quantum well layers. 
     
     
         3 . The device of  claim 2 , wherein at least one of the non-polar Group III nitride quantum well layers has a thickness greater than  5  nanometers and emits light having a peak photoluminescence (PL) emission wavelength and an intensity that are greater than a PL emission wavelength and an intensity of light emitted from a non-polar Group III nitride quantum well layer having a thickness of 5 nanometers or less. 
     
     
         4 . The device of  claim 1 , wherein the non-polar Group III nitride layers comprise one or more non-polar Group III nitride heterostructures. 
     
     
         5 . The device of  claim 4 , wherein at least one of the non-polar Group III nitride heterostructures contains a superlattice. 
     
     
         6 . The device of  claim 5 , wherein the superlattice produces an electrical channel for transistor operation. 
     
     
         7 . The device of  claim 1 , wherein the GaN substrate is a GaN template. 
     
     
         8 . The device of  claim 1 , wherein the GaN substrate has a threading dislocation density of no more than 2.6×10 10  cm −2 . 
     
     
         9 . The device of  claim 1 , wherein the GaN substrate has a stacking fault density of no more than 3.8×10 5  cm −1 . 
     
     
         10 . A method for fabricating a nitride semiconductor device, comprising:
 growing one or more non-polar Group III nitride layers on or above a non-polar surface of a Gallium Nitride (GaN) substrate, wherein the non-polar surface of the GaN substrate is a grown surface.   
     
     
         11 . The method of  claim 10 , wherein the non-polar Group III nitride layers comprise one or more non-polar Group III nitride quantum well layers. 
     
     
         12 . The method of  claim 11 , wherein at least one of the non-polar Group III nitride quantum well layers has a thickness greater than 5 nanometers and emits light having a peak photoluminescence (PL) emission wavelength and an intensity that are greater than a PL emission wavelength and an intensity of light emitted from a non-polar Group III nitride quantum well layer having a thickness of 5 nanometers or less. 
     
     
         13 . The method of  claim 10 , wherein the non-polar Group III nitride layers comprise one or more non-polar Group III nitride heterostructures. 
     
     
         14 . The method of  claim 13 , wherein at least one of the non-polar Group III nitride heterostructures contains a superlattice. 
     
     
         15 . The method of  claim 14 , wherein the superlattice produces an electrical channel for transistor operation. 
     
     
         16 . The method of  claim 10 , wherein the GaN substrate is a GaN template. 
     
     
         17 . The method of  claim 10 , wherein the GaN substrate has a threading dislocation density of no more than 2.6×10 10  cm −2 . 
     
     
         18 . The method of  claim 10 , wherein the GaN substrate has a stacking fault density of no more than 3.8×10 5  cm −1 .

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