Packaging structure

Abstract

A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

1 . A package structure, comprising:
 a circuit substrate, comprising a top surface and a bottom surface opposite to the top surface;   a first chip, disposed on the top surface of the circuit substrate, wherein the first chip has a top surface and a bottom surface opposite to each other, the bottom surface of the first chip faces the circuit substrate, the first chip has a plurality of through silicon vias, and an end of each of the through silicon vias protrudes from the top surface of the first chip;   a plurality of first bumps, disposed between the first chip and the circuit substrate and electrically connecting the through silicon vias with the circuit substrate;   a first molding compound, covering the top surface of the circuit substrate and having an opening exposing the top surface of the first chip and the end of each of the through silicon vias;   a second chip, disposed above the first chip, the second chip having a bottom surface facing the first chip, wherein a size of the second chip is greater than that of the first chip; and   a plurality of pillar bumps, disposed on the bottom surface of the second chip and electrically connecting the second chip with the corresponding through silicon vias wherein a top surface of the first molding compound has a height difference H 1  relative to the end of each of the through silicon vias, and a height H 2  of the pillar bumps is greater than the height difference H 1 .   
     
     
         2 . The package structure according to  claim 1 , further comprising a first underfill disposed between the first chip and the circuit substrate to encapsulate the first bumps. 
     
     
         3 . The package structure according to  claim 2 , wherein the first underfill comprises a thermal-cured material. 
     
     
         4 . The chip package as claimed in  claim 1 , further comprising a second molding compound disposed on the first molding compound and covering the second chip. 
     
     
         5 . The package structure according to  claim 4 , further comprising a first underfill disposed between the first chip and the circuit substrate to encapsulate the first bumps. 
     
     
         6 . The package structure according to  claim 5 , further comprising a second underfill disposed between the second chip and the first chip to encapsulate the pillar bumps and the end of each of the through silicon vias. 
     
     
         7 . The package structure according to  claim 1 , further comprising a second underfill disposed between the second chip and the first chip to encapsulate the pillar bumps and the end of each of the through silicon vias. 
     
     
         8 . The package structure according to  claim 7 , wherein the first underfill comprises a thermal-cured material. 
     
     
         9 . The package structure according to  claim 1 , wherein a lateral surface of the circuit substrate and a lateral surface of the first molding compound are coplanar with each other. 
     
     
         10 . The package structure according to  claim 4 , wherein a lateral surface of the circuit substrate, a lateral surface of the first molding compound, and a lateral surface of the second molding compound are coplanar with one another. 
     
     
         11 . The package structure according to  claim 1 , further comprises a plurality of solder balls disposed at a bottom of the circuit substrate. 
     
     
         12 . The package structure according to  claim 1 , wherein a periphery of the second chip is located above the top surface of the first molding compound. 
     
     
         13 . A package structure, comprising:
 a circuit substrate, comprising a top surface and a bottom surface opposite to the top surface;   a package unit, disposed on the top surface of the circuit substrate, the package unit comprising:
 a first chip, having a top surface and a bottom surface opposite to each other, the bottom surface of the first chip faces the circuit substrate, the first chip has a plurality of through silicon vias, and an end of each of the through silicon vias protrudes from the top surface of the first chip; 
 a first molding compound, covering the first chip, wherein a bottom surface of the first molding compound is coplanar with the bottom surface of the first chip, and the first molding compound has an opening exposing the top surface of the first chip and the end of each of the through silicon vias; 
 a plurality of first bumps, disposed between the first chip and the circuit substrate and electrically connecting the through silicon vias with the circuit substrate; 
 a second chip, disposed above the first chip, the second chip having a bottom surface facing the first chip, wherein a size of the second chip is greater than that of the first chip; and 
 a plurality of pillar bumps, disposed on the bottom surface of the second chip and electrically connecting the second chip with the corresponding through silicon vias, wherein a distance between the bottom surface of the second chip and the top surface of the first chip is greater than that between a top surface of the first molding compound and the top surface of the first chip. 
   
     
     
         14 . The package structure as claimed in  claim 13 , wherein a size of the circuit substrate is greater than that of the package unit. 
     
     
         15 . The package structure according to  claim 13 , further comprising a first underfill disposed between the package unit and the circuit substrate to encapsulate the first bumps. 
     
     
         16 . The package structure as claimed in  claim 13 , further comprising a second molding compound disposed on the first molding compound and covering the second chip. 
     
     
         17 . The package structure according to  claim 16 , further comprising a first underfill disposed between the package unit and the circuit substrate to encapsulate the first bumps. 
     
     
         18 . The package structure according to  claim 17 , further comprising a second underfill disposed between the second chip and the first chip to encapsulate the pillar bumps and the end of each of the through silicon vias. 
     
     
         19 . The package structure according to  claim 16 , wherein a lateral surface of the first molding compound and a lateral surface of the second molding compound are coplanar with each other. 
     
     
         20 . The package structure according to  claim 13 , further comprising a second underfill disposed between the second chip and the first chip to encapsulate the pillar bumps and the end of each of the through silicon vias.