Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer

Abstract

In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

1 .- 19 . (canceled) 
     
     
         20 . A semiconductor device, comprising:
 a gate electrode structure of a transistor formed above a semiconductor region, said gate electrode structure comprising a gate insulation layer including a high-k dielectric material and an electrode material formed on said gate insulation layer and having a tapered cross-sectional configuration; and   a dielectric material formed above said gate electrode structure and having an internal compressive stress level so as to induce a compressive strain in a channel region of said transistor.   
     
     
         21 . The semiconductor device of  claim 20 , further comprising a second gate electrode structure of a second transistor formed above a second semiconductor region, wherein said second gate electrode structure comprises a gate insulation layer including a high-k dielectric material and an electrode material formed on said gate insulation layer and having a tapering cross-sectional configuration and wherein a second dielectric material having a tensile stress level is formed above said second semiconductor region. 
     
     
         22 . The semiconductor device of  claim 20 , wherein a length of said electrode material at said gate insulation layer is approximately 30 nm or less. 
     
     
         23 . The semiconductor device of  claim 20 , further comprising a silicon and nitrogen-containing stress-relaxed dielectric material formed between said gate electrode structure and said dielectric material having said compressive stress level. 
     
     
         24 . The semiconductor device of  claim 23 , wherein at least a portion of said silicon and nitrogen-containing stress-relaxed dielectric material further comprises at least one of xenon or germanium. 
     
     
         25 . The semiconductor device of  claim 23 , wherein at least a portion of said silicon and nitrogen-containing stress-relaxed dielectric material is formed in said dielectric material. 
     
     
         26 . The semiconductor device of  claim 21 , further comprising a third dielectric layer formed between the first and second dielectric layers and above said semiconductor region and said second semiconductor region. 
     
     
         27 . The semiconductor device of  claim 26 , wherein said third dielectric layer comprises a tensile strain. 
     
     
         28 . The semiconductor device of  claim 20 , further comprising:
 a second gate electrode structure of a second transistor formed above a second semiconductor region, wherein said second gate electrode structure comprises a gate insulation layer including a high-k dielectric material and an electrode material formed on said gate insulation layer and having a tapering cross-sectional configuration; and   wherein said dielectric material is formed above said second gate electrode structure.   
     
     
         29 . The semiconductor device of  claim 28 , further comprising a second dielectric layer with a tensile strain. 
     
     
         30 . The semiconductor device of  claim 29 , wherein said second dielectric layer comprises a portion in which said tensile strain is stress-relaxed. 
     
     
         31 . The semiconductor device of  claim 28 , further comprising a silicon and nitrogen-containing stress-relaxed dielectric material formed between said first gate electrode structure and said first dielectric material having said compressive stress level 
     
     
         32 . A semiconductor device, comprising:
 a first gate electrode structure of a transistor formed above a first semiconductor region, said first gate electrode structure comprising a first gate insulation layer including a first high-k dielectric material and a first electrode material formed on said first gate insulation layer and having a tapered cross-sectional configuration;   a second gate electrode structure of a second transistor formed above a second semiconductor region, wherein said second gate electrode structure comprises a second gate insulation layer including a second high-k dielectric material and a second electrode material formed on said second gate insulation layer and having a tapering cross-sectional configuration;   a first dielectric material formed above said first and second gate electrode structures and having an internal compressive stress level so as to induce a compressive strain in a channel region of said first transistor; and   a second dielectric material formed above said first and second semiconductor regions and laterally adjacent to said first and second gate electrode structures, said second dielectric material having a tensile stress level so as to induce a tensile strain in a channel region of said second transistor.   
     
     
         33 . The semiconductor device of  claim 32 , wherein a length at least one of said first and second electrode materials at said respective first and second gate insulation layers is approximately 30 nm or less. 
     
     
         34 . The semiconductor device of  claim 32 , further comprising a silicon and nitrogen-containing stress-relaxed dielectric material formed between said first gate electrode structure and said first dielectric material. 
     
     
         35 . The semiconductor device of  claim 34 , wherein at least a portion of said silicon and nitrogen-containing stress-relaxed dielectric material further comprises at least one of xenon or germanium. 
     
     
         36 . The semiconductor device of  claim 35 , wherein forming said at least a portion of said silicon and nitrogen-containing stress-relaxed dielectric material comprising at least one of xenon or germanium includes performing an ion implantation process. 
     
     
         37 . The semiconductor device of  claim 34 , wherein at least a portion of said silicon and nitrogen-containing stress-relaxed dielectric material is formed in said first dielectric material. 
     
     
         38 . The semiconductor device of  claim 32 , further comprising a third dielectric layer formed between the first and second dielectric layers and above said first semiconductor region and said second semiconductor region. 
     
     
         39 . The semiconductor device of  claim 37 , wherein said third dielectric layer comprises a tensile strain. 
     
     
         40 . The semiconductor device of  claim 32 , wherein said second dielectric layer comprises a stress-relaxed portion.